Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate and a white OLED display unit on the base substrate, and further includes: an optical adjustment structure on a light emitting side of the white OLED display unit, where the optical adjustment structure is in a peripheral region of each pixel region. The optical adjustment structure is configured to absorb light in a first wavelength range or convert light in a first wavelength range into light in a second wavelength range.

Abstract: Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.

Abstract: A semiconductor device and its fabrication method are provided. The method includes forming a core layer on a first region of a base substrate layer; forming sidewall spacer layers on sidewalls of two sides of the core layer along a first direction; forming a filling layer on a second region between adjacent sidewall spacer layers which are arranged along the first direction; forming a first dividing trench in the filling layer on the second region to divide the filling layer along a second direction, where sidewalls of the first dividing trench, arranged along the first direction, expose corresponding sidewall spacer layers; forming a second dividing trench in the core layer to divide the core layer along the second direction; forming a second dividing layer in the second dividing trench when forming a first dividing layer in the first dividing trench; and removing the filling layer and the core layer.

Abstract: Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.

Abstract: A semiconductor device and its fabrication method are provided. The method includes forming a core layer on a first region of a base substrate layer; forming sidewall spacer layers on sidewalls of two sides of the core layer along a first direction; forming a filling layer on a second region between adjacent sidewall spacer layers which are arranged along the first direction; forming a first dividing trench in the filling layer on the second region to divide the filling layer along a second direction, where sidewalls of the first dividing trench, arranged along the first direction, expose corresponding sidewall spacer layers; forming a second dividing trench in the core layer to divide the core layer along the second direction; forming a second dividing layer in the second dividing trench when forming a first dividing layer in the first dividing trench; and removing the filling layer and the core layer.

Abstract: Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.

Abstract: Nanoparticulate carrier formulations are useful to solubilize, deliver, and target hydrophobic drugs for treating diseases including cancer and bacterial infections. The formulations contain amphiphilic peptides having a hydrophobic portion and a positively charged hydrophilic portion. The peptides self-associate at nonacidic pH to form mi-celles with a spherical nanoparticle morphology. The hydrophobic core of the nano-particles encapsulates hydrophobic drugs, including antitumor agents, increasing their solubility in water and allowing them to be targeted, for example, to cancer cells. The positively charged surface of the nanoparticles, together with an optional targeting moiety such as an RGD peptide, allows the nanoparticles to bind selectively to mammalian cells and bacterial cells, including cancer cells that overexpress integrin receptors.

Abstract: The present invention relates to crystalline forms of pyrroloquinoline quinone disodium salt. The present invention provides crystalline Form A and crystalline Form B of pyrroloquinoline quinone disodium salt, and the methods and uses for the preparation thereof. The X-ray powder diffraction patterns of crystalline Form A and crystalline Form B are as shown by FIG. 1 and FIG. 5, respectively. The crystalline forms of the present invention have low moisture absorption and high stability, as well as excellent use and storage performances.