Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a thin metal-organic layer on a copper structure, wherein the thin metal-organic layer substantially prevents corrosion of the copper structure, and wherein the thin metal-organic layer comprises an organo-copper compound comprising an alkyl group and a thiol group. In addition, methods of applying a high pH cleaning process using a surfactant to improve surface wetting in a low foaming solution is described.

Abstract: The single substrate thermal processing apparatus (2) includes a process chamber (5) arranged to accommodate a target substrate (W) and provided with a showerhead (10) disposed on its ceiling. A support member (28) is disposed to support the target substrate (W) so as for it to face the showerhead (10), when the target substrate (W) is subjected to a semiconductor process. A heating lamp (30) is disposed below the support member (28), for radiating light to heat the target substrate (W). The support member (28) and heating lamp (30) are moved up and down together relative to the showerhead (10) by an elevator mechanism (20). The elevator mechanism (20) sets different distances between the showerhead (30) and heating lamp (10), in accordance with the different process temperatures, thereby causing temperature change of the bottom surface of the showerhead (10) to fall in a predetermined range.

Abstract: The single substrate thermal processing apparatus (2) includes a process chamber (5) arranged to accommodate a target substrate (W) and provided with a showerhead (10) disposed on its ceiling. A support member (28) is disposed to support the target substrate (W) so as for it to face the showerhead (10), when the target substrate (W) is subjected to a semiconductor process. A heating lamp (30) is disposed below the support member (28), for radiating light to heat the target substrate (W). The support member (28) and heating lamp (30) are moved up and down together relative to the showerhead (10) by an elevator mechanism (20). The elevator mechanism (20) sets different distances between the showerhead (30) and heating lamp (10), in accordance with the different process temperatures, thereby causing temperature change of the bottom surface of the showerhead (10) to fall in a predetermined range.

Abstract: A transfer apparatus (42) for a semiconductor processing system includes a transfer member (44) having a support portion (48) to place a target substrate (W) thereon, and a drive unit (68) for driving the transfer member (44). A reference mark (54) is disposed adjacent to the support portion (48). The target substrate (W) has optically observable first and second portions (84, 86). A storage section (63) stores a normal image that shows a positional correlation between the reference mark (54) and the first and second portions (84, 86), obtained when the target substrate (W) is placed on the support portion (48) at a normal position. An image pick-up device (62A) takes a detection image that shows a positional correlation between the reference mark (54) and the first and second portions (84, 86), when the transfer member (44) transfers the target substrate (W).

Abstract: A transfer apparatus (42) for a semiconductor processing system includes a transfer member (44) having a support portion (48) to place a target substrate (W) thereon, and a drive unit (68) for driving the transfer member (44). A reference mark (54) is disposed adjacent to the support portion (48). The target substrate (W) has optically observable first and second portions (84, 86). A storage section (63) stores a normal image that shows a positional correlation between the reference mark (54) and the first and second portions (84, 86), obtained when the target substrate (W) is placed on the support portion (48) at a normal position. An image pick-up device (62A) takes a detection image that shows a positional correlation between the reference mark (54) and the first and second portions (84, 86), when the transfer member (44) transfers the target substrate (W).