Abstract: An interference-resistant wireless audio system includes a transceiver for transforming an audio signal into an RF signal, and a receiver for receiving RF signals in the air. The transceiver has an audio signal receiver, an audio data format converter, a frame and coding unit, a modulation module, an RF transceiver, a receiving/transmitting switch controller, an RF signal detector, and a channel switch controller electrically connected to the RF signal detector for controlling the RF transceiver to switch the used channel to another one after receiving a switch signal generated by the RF signal detector.

Abstract: A core logic circuit which works with a CPU and a main graphics accelerator in a computer system is provided. The core logic chip includes a host controller electrically connected to the CPU for receiving a command from the CPU; an auxiliary graphing engine electrically connected to the host controller for receiving and processing the command; and a transmission controller electrically connected to the auxiliary graphing engine for transmitting the command that is processed and outputted by the auxiliary graphing engine to the main graphics accelerator to be further processed.

Abstract: An interference-resistant wireless audio system includes a transceiver for transforming an audio signal into an RF signal, and a receiver for receiving RF signals in the air.

Abstract: A method is adapted for compressing an image data block, and includes the steps of: (a) subjecting the image data block to discrete cosine transformation so as to generate discrete cosine transform data; (b) quantizing the discrete cosine transform data in accordance with a quantizer matrix that consists of an array of quantizing coefficients so as to generate quantized data; (c) encoding the quantized data using an entropy coding algorithm so as to generate an encoded bitstream; and (d) when the length of the encoded bitstream does not fall within a predetermined range, adjusting the quantizing coefficients in the quantizer matrix and repeating steps (b) and (c) until the length of the encoded bitstream falls within the predetermined range.

Abstract: The present invention discloses a method for accelerated triangle occlusion culling in the computer graphic system. The triangle-based visibility testing is determined by using a triangle within a particular group of Coarse-Z buffer. If the triangle within a particular group of Coarse-Z buffer is hidden, then the triangle will be discarded. By using triangle-based visibility pre- test determined by the Coarse-Z buffer, the graphics system can skip hidden surface at a great lick and the requirement of memory bandwidth and unnecessary computations is eliminated.

Abstract: A core logic circuit for use with a CPU and a main graphics accelerator in a computer system is provided. The core logic chip includes a host controller electrically connected to the CPU for receiving a command from the CPU; an auxiliary graphing engine electrically connected to the host controller fore receiving and processing the command; and a transmission controller electrically connected to the auxiliary graphing engine for transmitting the command processed and outputted by the auxiliary graphing engine to the main graphics accelerator to be further processed.

Abstract: A method is adapted for compressing an image data block, and includes the steps of: