Abstract: A backplane, a display device and a method of manufacturing a backplane are provided. The backplane includes a base substrate; an inorganic layer on the base substrate, the inorganic layer including a plurality of protrusions; a metal layer covering atop of each protrusion and partial side wall near the top, the metal layer covering adjacent protrusions being disconnected; and a light-emitting layer covering the metal layer and the inorganic layer between the adjacent protrusions, the light-emitting layer being disconnected at regions of the protrusions not covered by the metal layer.

Abstract: A backplane, a display device and a method of manufacturing a backplane are provided. The backplane includes a base substrate; an inorganic layer on the base substrate, the inorganic layer including a plurality of protrusions; a metal layer covering atop of each protrusion and partial side wall near the top, the metal layer covering adjacent protrusions being disconnected; and a light-emitting layer covering the metal layer and the inorganic layer between the adjacent protrusions, the light-emitting layer being disconnected at regions of the protrusions not covered by the metal layer.

Abstract: The present document discloses a synchronization method, herein the method includes a controller determining synchronization link topology information according to physical link topology information of the synchronous network and synchronization information of a synchronous node in the synchronous network; the controller generating a synchronization rule of the synchronous node according to the synchronization link topology information; and the controller transmitting the synchronization rule and/or a request message to the synchronous node in the synchronous network according to the synchronization link topology information. The present document further discloses a controller, a synchronous node, a synchronous network, and a storage medium.

Abstract: The present document discloses a synchronization method, herein the method includes a controller determining synchronization link topology information according to physical link topology information of the synchronous network and synchronization information of a synchronous node in the synchronous network; the controller generating a synchronization rule of the synchronous node according to the synchronization link topology information; and the controller transmitting the synchronization rule and/or a request message to the synchronous node in the synchronous network according to the synchronization link topology information. The present document further discloses a controller, a synchronous node, a synchronous network, and a storage medium.

Abstract: A TFT array substrate is disclosed. The substrate includes a plurality of gate lines, and a first gate drive circuit, where the first gate drive circuit includes m levels of first repeat units. Each level of first repeat unit includes a first shift register. The substrate also includes a second gate drive circuit, where the second gate drive circuit includes n levels of second repeat units. Each level of second repeat unit includes a second shift register. The substrate also includes a first start signal line and a first start transistor, where a drain of the first start transistor is electrically connected with the first start signal line. The substrate also includes a second start transistor, where a drain of the second start transistor is electrically connected with the first start signal line.

Abstract: A TFT array substrate is disclosed. The substrate includes a plurality of gate lines, and a first gate drive circuit, where the first gate drive circuit includes m levels of first repeat units. Each level of first repeat unit includes a first shift register. The substrate also includes a second gate drive circuit, where the second gate drive circuit includes n levels of second repeat units. Each level of second repeat unit includes a second shift register. The substrate also includes a first start signal line and a first start transistor, where a drain of the first start transistor is electrically connected with the first start signal line. The substrate also includes a second start transistor, where a drain of the second start transistor is electrically connected with the first start signal line.

Abstract: A TFT array substrate is disclosed. The substrate includes a plurality of gate lines, and a first gate drive circuit, where the first gate drive circuit includes m levels of first repeat units. Each level of first repeat unit includes a first shift register. The substrate also includes a second gate drive circuit, where the second gate drive circuit includes n levels of second repeat units. Each level of second repeat unit includes a second shift register. The substrate also includes a first start signal line and a first start transistor, where a drain of the first start transistor is electrically connected with the first start signal line. The substrate also includes a second start transistor, where a drain of the second start transistor is electrically connected with the first start signal line.

Abstract: A method and device for implementing a compensation for an asymmetry delay of a 1588 link are provided. The method comprises: measuring and calculating a value of an asymmetry delay of the 1588 uplink/downlink; performing an asymmetry delay compensation when the value of the asymmetry delay exceeds a set synchronization offset range; and continuing a normal 1588 time synchronization if the value of the asymmetry delay does not exceed the set synchronization offset range; and implementing the automatic compensation for the asymmetry delay of the 1588 link. The above-mentioned scheme can correct the asymmetry delay automatically, and ensure the quality of 1588 time synchronization.

Abstract: A TFT array substrate is disclosed. The array substrate includes gate lines, first and second gate driving circuits, first, second, third, and fourth clock signal lines, first and second initial signal lines, first and second initial transistors, and first, second, third, and fourth clock transistors. The first gate driving circuit includes m stages of first repeating units. The second gate driving circuit includes n stages of second repeating units. Where m and n are positive integers, and 2?m, 2?n.

Abstract: A method and system for detecting at ouch contact on an in-cell capacitive touch screen includes, based on the different gray scale pictures displayed by the in-cell capacitive touch screen in a non-touch state as well as a distribution of the intersections of rows and columns of the in-cell capacitive touch screen, obtaining noise values corresponding to different gray scales for each intersection, obtaining a theoretical noise value for each intersection under a condition of a current picture, and, for each intersection, compensating a detected signal with the theoretical noise value in the current picture to locate a position of the touch contact.

Abstract: A TFT array substrate is disclosed. The substrate includes a plurality of gate lines, and a first gate drive circuit, where the first gate drive circuit includes m levels of first repeat units. Each level of first repeat unit includes a first shift register. The substrate also includes a second gate drive circuit, where the second gate drive circuit includes n levels of second repeat units. Each level of second repeat unit includes a second shift register. The substrate also includes a first start signal line and a first start transistor, where a drain of the first start transistor is electrically connected with the first start signal line. The substrate also includes a second start transistor, where a drain of the second start transistor is electrically connected with the first start signal line.

Abstract: A TFT array substrate is disclosed. The array substrate includes gate lines, first and second gate driving circuits, first, second, third, and fourth clock signal lines, first and second initial signal lines, first and second initial transistors, and first, second, third, and fourth clock transistors. The first gate driving circuit includes m stages of first repeating units. The second gate driving circuit includes n stages of second repeating units. Where m and n are positive integers, and 2?m, 2?n.

Abstract: A control circuit of a touch display panel is disclosed. The control circuit includes a data signal source, a plurality of data signal lines, and a first control circuit. A scan period of the touch display panel includes a display period and a touch scan period. The first control circuit is configured to connect the data signal lines with the data signal source during the display period, and the first control circuit is configured to disconnect the data signal lines from the data signal source during the touch scan period.

Abstract: A method and device for implementing a compensation for an asymmetry delay of a 1588 link are provided. The method comprises: measuring and calculating a value of an asymmetry delay of the 1588 uplink/downlink; performing an asymmetry delay compensation when the value of the asymmetry delay exceeds a set synchronization offset range; and continuing a normal 1588 time synchronization if the value of the asymmetry delay does not exceed the set synchronization offset range; and implementing the automatic compensation for the asymmetry delay of the 1588 link. The above-mentioned scheme can correct the asymmetry delay automatically, and ensure the quality of 1588 time synchronization.

Abstract: A method and system for detecting at ouch contact on an in-cell capacitive touch screen includes, based on the different gray scale pictures displayed by the in-cell capacitive touch screen in a non-touch state as well as a distribution of the intersections of rows and columns of the in-cell capacitive touch screen, obtaining noise values corresponding to different gray scales for each intersection, obtaining a theoretical noise value for each intersection under a condition of a current picture, and, for each intersection, compensating a detected signal with the theoretical noise value in the current picture to locate a position of the touch contact.

Abstract: A capacitive position transducer for detecting position changes or producing position feedback signals in a servorecorder comprises a rhombic transmitter electrode connected to a voltage source and a plurality of rectangular receiver electrodes insulated from and adjacent to each other. Current flowing through the coupled transmitter and receiver electrodes is rectified by diode circuits and flows through a circuit of serially connected resistors, thereby forming an output voltage signal at an end of the resistor circuit. The linearity of the output voltage signal can be changed by changing the value of the resistors in the resistor circuit. The capacitive position transducer can also provide commutating signals required by brushless linear motor.