Abstract: An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

Abstract: A component for use in a semiconductor processing chamber is provided. A process exposed coating is on a surface of a component body, wherein the process exposed coating comprises at least one of YF3, MgF2, CeF4, HfF4, and LaF3, and wherein the process exposed coating has a thickness in a range of 10 nm to 290 nm.

Abstract: A component for use in a semiconductor processing chamber is provided. A component body of a metal or metal alloy has a process facing surface. An intermediate aluminum oxide coating is on the process facing surface, wherein the intermediate aluminum oxide coating is at least 99% pure by weight and has a porosity of less than 0.1% by volume, and wherein the intermediate aluminum oxide coating has a first thickness. A process exposed layer is on the intermediate aluminum oxide coating, wherein the process exposed layer comprises at least one of yttrium, hafnium, zirconium, lanthanum, magnesium, and a lanthanide, and wherein the process exposed layer is at least 99% pure by weight and has a porosity of less than 0.1% and has a second thickness, wherein the second thickness is less than or equal to the first thickness.

Abstract: A multi-sensor fusion method and system for intelligent driving vehicles are provided, which relate to the technical field of intelligent driving vehicles. The method includes: establishing an extended target tracker based on a GM-PHD algorithm and a rectangular target model of a detected object; processing detection information of a millimeter-wave radar by using the extended target tracker to obtain millimeter-wave radar track information of the detected object; processing detection information of a laser radar by using the established bounding-box detector and a JPDA tracker provided with an IMM-UKF to obtain laser-radar track information of the detected object; processing the millimeter-wave radar track information and the laser-radar track information by performing time-space conversion to obtain a central fusion node; and processing the central fusion node by using an IMF algorithm to obtain global track information.

Abstract: A SiC power device cell having double gate trenches with a first gate channel region of a SiC MOSFET formed along at least one sidewall of a first type gate trench connecting to a first source region, and a second gate channel region of a SiC SBR which is a MOS channel diode formed along a sidewall of a second type gate trench connecting to a second source region to inactivate a parasitic body diode for the turn-off switching loss reduction. A first P-shield region surrounds a bottom region of the second type gate trench and is connected to a source metal through a sidewall P type region, and a second P-shield region adjoins a lower surface of the first body region forming a saturation current pinching region with an adjacent second P-shield region for short circuit capability enhancement and gate oxide electric field reduction.

Abstract: A SiC trench power device comprises at least one SiC MOSFET and a SiC super barrier rectifier (SBR) integrated together in each unit cell having at least one-step gate trench structure for the SiC MOSFET. The at least one step gate trench comprising a first top gate trench and at least one first bottom gate trench; the first top gate trench has a trench width larger than that of the at least one first bottom gate trench; a gate electrode of the SiC MOSFET is disposed in the first top gate trench surrounded with a first insulating film on a bottom region of the first top gate trench, and surrounded with a first gate oxide on sidewalls of the top step gate trench; the first insulating film fills up the at least one first bottom gate trench having a thickness greater than that of the first gate oxide; and a Y-shape grounded P-shield region surrounds the at least one first bottom gate trench for the first gate oxide electric field reduction and short circuit capability enhancement.

Abstract: In examples, a query management system maintains a query schema for a structured data source. The query schema includes a collection of query templates, where each query template specifies at least one condition. When a mutation in an underling data source is detected, the query management system generates an invalidation command for a corresponding set of cached keys. Based on attributes of the mutated data set, the query template can enable the use of wildcard designations to for purpose of identifying cache keys that are to be invalidated as a result of the mutated data set.

Abstract: A SiC power device cell having a first gate channel region of a SiC MOSFET formed along a first gate trench sidewall of a gate trench connecting to a first source region, and a second gate channel region of a SiC SBR which is a MOS channel diode formed along the gate trench bottom connecting to a second source region to inactivate a parasitic body diode for turn-off switching loss reduction. A P-shield region and a second source region surrounding a second gate trench sidewall and a portion of the gate trench bottom to form the second gate channel region and to reduce the gate oxide electric field.

Abstract: The present disclosure provides a thin film transistor and a manufacturing method therefor, an array substrate, and a display panel. The thin film transistor includes a substrate and an active layer and a first gate electrode both located on the substrate. The active layer includes a first film layer and a second film layer stacked on the substrate, the second film layer is located between the first film layer and the first gate electrode, the first film layer and the second film layer are semiconductor film layers, the second film layer has a lower mobility than the first film layer, and the second film layer has a larger density than the first film layer.

Abstract: A copolymer, a preparation method therefor, vulcanized rubber and a use thereof are provided. The copolymer contains a polyethylene segment and a butadiene rubber segment. Based on the total weight of the copolymer, the weight ratio of the polyethylene chain segment to the butadiene rubber chain segment is 0.1:99.9-80:20. In the butadiene rubber chain segment, based on the total amount of the butadiene rubber chain segment, the content of cis-1,4-structure is 90-98.5 mol %. The continuous methylene sequence length in the copolymer is at least 165. By means of synthesizing the copolymer by using in-situ polymerization, a polyethylene butadiene rubber block copolymer has a compatibilization effect, the dissolution of a reinforcement polyethylene phase and a butadiene rubber matrix is facilitated, a copolymer with excellent dispersibility of reinforced filler can be obtained without later compounding.

Abstract: A SiC trench MOSFET with an embedded junction Schottky barrier diode (JBSD) having P-shield (PS) regions surrounding bottoms of source-body-Schottky contact (SBSC) trenches for gate oxide electric-field and switching loss reductions is disclosed. A source metal connects with the PS regions and the JBSD directly. Sidewall P (SP) regions are formed along a portion of sidewalls of the SBSC trenches to improve a tradeoff between a drain-source leakage current of the SiC trench MOSFET and a forward voltage of the JBSD. The device further comprises an N-type shield region formed below each of gate trenches for gate oxide electric field strength and specific on-resistance reductions.

Abstract: A component for use in a plasma processing chamber system is provided. A component body has a plasma facing surface. The plasma facing surface comprises a pyrochlore, comprising at least one of zirconium and hafnium and at least one of lanthanum (La), samarium (Sm), yttrium (Y), erbium (Er), cerium (Ce), gadolinium (Gd), ytterbium (Yb), and neodymium (Nd).

Abstract: An integrated circuit comprising a SiC MOSFET and a SiC super barrier rectifier (SBR) disposed in one unit cell having an asymmetric trench gate electrode structure formed in a stripe gate trench is disclosed. A first channel region of the SiC MOSFET is formed along a first trench sidewall of the gate trench while a second channel region of the SiC SBR is formed along a first portion of a second trench sidewall opposite to the first trench sidewall of the gate trench. A source metal connects with a source region, body regions, and the gate electrode of the SiC SBR directly, and connects with a P-shield (PS) region below the gate trench through a grounded P (GP) region along a second portion of the second gate trench sidewall.

Abstract: A component in a semiconductor processing chamber is provided. An electrically conductive semiconductor or metal body has a CTE of less than 10.0×10?6/K. An intermediate layer is disposed over at least one surface of the body, the intermediate layer comprising a fluoropolymer. A perfluoroalkoxy alkane (PFA) layer is disposed over the intermediate layer to form the component.

Abstract: A method for conditioning a component of a wafer processing chamber is provided. The component is placed in an ultrasonic conditioning solution in an ultrasonic solution tank. Ultrasonic energy is applied through the ultrasonic conditioning solution to the component to clean the component. The component is submerged in a megasonic conditioning solution in a tank. Megasonic energy is applied through the megasonic conditioning solution to the component to clean the component.

Abstract: A divalent metal complex such as a divalent platinum complex, preparation method and use thereof, and an organic optoelectronic device containing the complex are provided. The divalent metal complex is of formula (I). The divalent metal complex has a green light wavelength peak of 515-535 nm, with CIE covering well the green light region.

Abstract: Liquid polybutadiene, and a preparation method therefor and an application thereof are provided. The liquid polybutadiene has a number-average molecular weight of 2,500-5,500 and a molecular weight distribution index of 1-1.2. Based on the total amount of the liquid polybutadiene, the content of a 1,2-structural unit in the liquid polybutadiene is 85-95 wt %, the content of a 1,4-structural unit in the liquid polybutadiene is 5-15 wt %, and the molar ratio of a cis-1,4-structural unit to a trans-1,4-structural unit in the liquid polybutadiene is 1-2:1; and the dynamic viscosity of the liquid polybutadiene at 45° C. is 100-500 P. The liquid polybutadiene has good flowability, good film formability, and good coating performance, and a formed coating has an improved adhesion force to a substrate.

Abstract: In examples, a query management system maintains a query schema for a structured data source. The query schema includes a collection of query templates, where each query template specifies at least one condition. When a mutation in an underling data source is detected, the query management system generates an invalidation command for a corresponding set of cached keys. Based on attributes of the mutated data set, the query template can enable the use of wildcard designations to for purpose of identifying cache keys that are to be invalidated as a result of the mutated data set.

Abstract: A component for use in a semiconductor processing chamber is provided. A component body has a process facing surface, wherein the component body comprises at least one of iron, iron alloy, nickel, nickel alloy, titanium, and titanium alloy. A coating is over the process facing surface, wherein the coating comprises at least one of a metal oxide, a metal fluoride, and a metal oxyfluoride, wherein the coating is at least 99% by weight pure and has a porosity of less than 0.1%.

Abstract: A chuck system for supporting a substrate in a plasma processing chamber is provided. A base plate comprises a substrate support region and a shoulder surrounding the substrate support region. A protective coating is on a surface of the base plate, wherein the protective coating covers at least part of the shoulder. A layer of a silane coupling agent is on the protective coating.