Abstract: A large-tonnage disc-shaped suspension ceramic insulator includes a ceramic insulator body, and a metal pin and a metal cap coaxially assembled with the ceramic insulator body through adhesive material, assembly interfaces of the ceramic insulator body, the metal cap, and the metal pin are coated with a primer; the adhesive material includes an expansion agent; and the expansion agent is configured to make the adhesive material expand after hardening so as to create a prestress between the ceramic insulator body and the metal pin as well as the metal cap. The present disclosure achieves overall compressive prestress distribution of the ceramic insulator product, mitigating thermal stress caused by temperature changes and improving the tensile strength of the large-tonnage disc-shaped suspension ceramic insulator assembly. By treating the assembly interfaces with the primer, the present disclosure significantly improves the assembly strength of the ceramic insulator/metal assembly.

Abstract: The present application provides a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. Two semiconductor layers having different carrier mobilities are provided, the semiconductor layer having a lower carrier mobility covers the semiconductor layer having a higher carrier mobility, and the semiconductor layer having a higher carrier mobility is located within the coverage area of a first electrode.

Abstract: A component of a plasma processing chamber is provided. A yttria coating is formed on a surface of a component body, wherein the yttria coating is deposited by aerosol deposition and is annealed, wherein the yttria coating is at least 95% pure yttria by weight.

Abstract: A SiC trench MOSFET with an embedded junction Schottky barrier diode (JBSD) having P-shield (PS) regions surrounding bottoms of source-body-Schottky contact (SBSC) trenches for gate oxide electric-field and switching loss reductions is disclosed. A source metal connects with the PS regions and the JBSD directly. Sidewall P (SP) regions are formed along a portion of sidewalls of the SBSC trenches to improve a tradeoff between a drain-source leakage current of the SiC trench MOSFET and a forward voltage of the JBSD. The device further comprises an N-type shield region formed below each of gate trenches for gate oxide electric field strength and specific on-resistance reductions.

Abstract: A multi-sensor fusion method and system for intelligent driving vehicles are provided, which relate to the technical field of intelligent driving vehicles. The method includes: establishing an extended target tracker based on a GM-PHD algorithm and a rectangular target model of a detected object; processing detection information of a millimeter-wave radar by using the extended target tracker to obtain millimeter-wave radar track information of the detected object; processing detection information of a laser radar by using the established bounding-box detector and a JPDA tracker provided with an IMM-UKF to obtain laser-radar track information of the detected object; processing the millimeter-wave radar track information and the laser-radar track information by performing time-space conversion to obtain a central fusion node; and processing the central fusion node by using an IMF algorithm to obtain global track information.

Abstract: A website misclassification report is received. A determination is made that a current classification model correctly classifies a website. The current classification model is different from a model that was previously used to classify the website. In response to a determination that the website is correctly classified by the current classification model, a reclassification operation is performed, using the current classification model, on a second website.

Abstract: A thin film transistor and a preparation method thereof, a display panel, and a display device. The thin film transistor includes an active structure and a gate that are stacked and insulated by an interlayer insulating layer, the active structure includes a source region, a drain region, and a channel region, the source region and the drain region are located on two sides of the channel region, and in a thickness direction of the interlayer insulating layer, a projection of the gate overlaps with a projection of the channel region; wherein the channel region includes a metal oxide material, a ratio of a number of indium atoms and a number of zinc atoms in the channel region is a, and a?4.

Abstract: A component of a plasma processing chamber having at least one plasma facing surface of the component comprises single crystal metal oxide material. The component can be machined from a single crystal metal oxide ingot. Suitable single crystal metal oxides include spinel, yttrium oxide, and yttrium aluminum garnet (YAG). A single crystal metal oxide can be machined to form a gas injector of a plasma processing chamber.

Abstract: The disclosure relates to the field of display technologies, and in particular, to a thin film transistor, a display panel, and a display apparatus. The thin film transistor includes: an active layer provided on a substrate. The active layer includes a first semiconductor layer, a first barrier layer, and a second semiconductor layer stacked in sequence. The first semiconductor layer is located on a side, away from the substrate, of the second semiconductor layer, and a mobility rate of the first semiconductor layer is less than a mobility rate of the second semiconductor layer. A double channel is formed by providing the first barrier layer provided between the first semiconductor layer and the second semiconductor layer, so as to make a threshold voltage Vth positive and improve the mobility rate of the thin film transistor, so that a greater processing Margin may be accommodated, thereby ensuring stability of a device.

Abstract: An improved SiC trench MOSFET having N-type and P-type shield zones for gate oxide electric-field reduction is disclosed. The N-type shield zones are formed below a gate electrode and the P-type shield zones adjoin lower surfaces of the body regions. The device further comprises a current spreading region surrounding at least sidewalls of the gate trenches for on-resistance reduction.

Abstract: Methods and systems for budgeted and simplified training of deep neural networks (DNNs) are disclosed. In one example, a trainer is to train a DNN using a plurality of training sub-images derived from a down-sampled training image. A tester is to test the trained DNN using a plurality of testing sub-images derived from a down-sampled testing image. In another example, in a recurrent deep Q-network (RDQN) having a local attention mechanism located between a convolutional neural network (CNN) and a long-short time memory (LSTM), a plurality of feature maps are generated by the CNN from an input image. Hard-attention is applied by the local attention mechanism to the generated plurality of feature maps by selecting a subset of the generated feature maps. Soft attention is applied by the local attention mechanism to the selected subset of generated feature maps by providing weights to the selected subset of generated feature maps in obtaining weighted feature maps.

Abstract: An apparatus adapted for use in a plasma processing chamber is provided. An aluminum body with at least one surface is provided. An aluminum oxide containing aerosol deposition coating is disposed over the at least one surface of the aluminum body. An yttrium containing aerosol deposition coating is disposed over the aluminum oxide containing aerosol deposition coating.

Abstract: An electronic device includes a first body, a second body, and a linkage control assembly. The linkage control assembly includes a rotation shaft, a position-limiting linkage member, and a position-limiting mating member. The rotation shaft is configured to rotatably connect the first body and the second body. The position-limiting linkage member is arranged at the rotation shaft. The position-limiting mating member is arranged at a side of the rotation shaft close to the first body. The position-limiting linkage member is configured to cooperate with the position-limiting mating member to perform position-limiting on the rotation angle of the second body. The position-limiting linkage member rotates based on an extension length and/or a weight increase value along a first direction. The position-limiting linkage member rotates along a second direction based on the retraction length of the second body and/or a weight decrease value.

Abstract: Shielded gate devices having a planarized thermally grown (PTG) inter-poly oxide (IPO) structure are disclosed. By using a method having double wet etching processes of a field oxide and double dry etching processes of a first doped polysilicon, the PTG IPO structure is achieved to reduce gate-source leakage current Igss and gate resistance Rg. A gate oxide and a PTG IPO are thermally grown simultaneously. The devices further comprise a current spreading region surrounding a lower portion of a gate electrode for on-resistance reduction.

Abstract: A method for conditioning a component of a wafer processing chamber is provided. The component is placed in an ultrasonic conditioning solution in an ultrasonic solution tank. Ultrasonic energy is applied through the ultrasonic conditioning solution to the component to clean the component. The component is submerged in a megasonic conditioning solution in a tank. Megasonic energy is applied through the megasonic conditioning solution to the component to clean the component.

Abstract: A SiC shielded gate trench device having a first type gate trench and a second type gate trench is disclosed. The first type gate trench is above the second type gate trench and has a trench width wider than a trench width of the second type gate trench, wherein the first type gate trench is filled with a gate electrode and a shielded gate electrode, and a grounded P-shield region surrounding the second type gate trench is under the shielded gate electrode for gate oxide electric-field reduction. The device further comprises a current spreading region surrounding the gate electrode for on-resistance reduction.

Abstract: The present disclosure is directed to electrolyte membrane compositions, electrolyte membranes, batteries utilizing said electrolyte membranes, and methods of assembling said batteries. The electrolyte membranes disclosed herein provide membranes and electrolytes for sustainable and more robust batteries.

Abstract: A method for making a component for use in a semiconductor processing chamber is provided. A component body is formed from a conductive material having a coefficient of thermal expansion of less than 10.0×10?6/K. A metal oxide layer is then disposed over a surface of the component body.

Abstract: A SGT MOSFET and a SGT super barrier rectifier having improved on-resistance and gate charge structures are disclosed in this invention by applying a short channel implant region for formation of a shorter channel length after body implantation and diffusion, and by introducing a super junction region below an oxide charge balance region for breakdown voltage enhancement. The present invention can further achieve a lower specific on-resistance by applying multiple stepped epitaxial layers or multiple stepped oxide structure.

Abstract: A method for treating a ceramic component for use in a semiconductor processing chamber, wherein the ceramic component comprises a ceramic laminate comprising a base zone comprising a first dielectric ceramic material, a protective, wherein the protective zone comprises a second dielectric ceramic material, and a transition zone between the protective zone and base zone, wherein the transition zone comprises the first dielectric ceramic material and the second dielectric ceramic material, wherein exposure of the ceramic component to UV light changes an optical property of at least a first part of the ceramic component is provided. A heat treatment of the ceramic component is provided by heating the ceramic component in a furnace to a temperature of between 400° C. to 1000° C. for a period between 2 hours to 20 hours, wherein the heat treatment changes the optical property of the first part of the ceramic component.