Abstract: The present disclosure provides embodiments of a semiconductor structure having bi-layer self-aligned contact. The semiconductor structure includes a gate stack disposed on a semiconductor substrate and having a first height, a spacer disposed on a sidewall of the gate stack and having a second height greater than the first height, and a first etch stop layer disposed on a sidewall of the gate spacer and having a third height greater than the second height. The semiconductor structure further includes a first dielectric layer disposed over the gate stack and contacting the gate spacer and the first etch stop layer and a second dielectric layer disposed on the first dielectric layer and contacting the first etch stop layer.

Abstract: A method includes providing a structure having a gate stack; first gate spacers; a second gate spacer over one of the first gate spacers and having an upper portion over a lower portion; a dummy spacer; an etch stop layer; and a dummy cap. The method further includes removing the dummy cap, resulting in a first void above the gate stack and between the first gate spacers; removing the dummy spacer, resulting in a second void above the lower portion and between the etch stop layer and the upper portion; depositing a layer of a decomposable material into the first and the second voids; depositing a seal layer over the etch stop layer, the first and the second gate spacers, and the layer of the decomposable material; and removing the layer of the decomposable material, thereby reclaiming at least portions of the first and the second voids.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

Abstract: A method includes providing a structure having a substrate, a first dielectric layer over the substrate, one or more semiconductor channel layers over the first dielectric layer and connecting a first source/drain (S/D) feature and a second S/D feature, and a gate structure engaging the one or more semiconductor channel layers; etching the substrate from the backside of the structure to form a first trench exposing the first S/D feature and a second trench exposing the second S/D feature; forming an S/D contact in the first trench; etching at least a portion of the first dielectric layer resulting in a portion of the S/D contact protruding from the first dielectric layer at the backside of the structure; and depositing a seal layer over the S/D contact, wherein the seal layer caps an air gap between the gate structure and the seal layer.

Abstract: A method includes forming a first dummy gate and a second dummy gate over a fin that protrudes above a substrate; replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively; forming a dielectric cut pattern between the first and the second metal gates, the dielectric cut pattern extending further from the substrate than the first and the second metal gates; forming a patterned mask layer over the first metal gate, the second metal gate, and the dielectric cut pattern, an opening in the patterned mask layer exposing a portion of the first metal gate, a portion of the second metal gate, and a portion of the dielectric cut pattern underlying the opening; filling the opening with a first electrically conductive material; and recessing the first electrically conductive material below an upper surface of the dielectric cut pattern.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack wrapping around a first upper portion of the fin. The semiconductor device structure includes a first stressor and a second stressor respectively over opposite first sides of the fin. The semiconductor device structure includes a spacer structure between the gate stack and the first stressor. The semiconductor device structure includes a first spacer layer covering a sidewall of the gate stack, the spacer structure, and the first stressor. The semiconductor device structure includes a dielectric layer over the first spacer layer. The semiconductor device structure includes an etch stop layer between the first spacer layer and the dielectric layer. The semiconductor device structure includes a seal structure between the second upper portion and the third upper portion.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a contact over a fin structure, a gate spacer layer between the gate stack and the contact, a first mask layer over the gate stack, and a second mask layer over the contact. The first mask layer includes a protruding portion sandwiched between an upper portion of the second mask layer and the gate spacer layer.

Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.

Abstract: Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.

Abstract: A method includes providing a structure having a substrate, a fin, source/drain (S/D) features, an isolation structure adjacent to sidewalls of the fin, one or more channel layers over a first dielectric layer and connecting the S/D features, and a gate structure engaging the one or more channel layers. The method further includes thinning down the structure from its backside until the fin is exposed and selectively etching the fin to form a trench that exposes surfaces of the S/D features, the first dielectric layer, and the isolation structure. The method further includes forming a silicide feature on the S/D features and depositing an inhibitor on the silicide feature but not on the surface of the first dielectric layer and the isolation structure, depositing a dielectric liner layer on the surfaces of the isolation structure and the first dielectric layer but not on the inhibitor, and selectively removing the inhibitor.

Abstract: Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed.

Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.

Abstract: A method includes providing a structure having a substrate, a gate, a gate spacer, a dielectric gate cap, a source/drain (S/D) feature, a contact etch stop layer (CESL) covering a sidewall of the gate spacer and a top surface of the S/D feature, and an inter-level dielectric (ILD) layer. The method includes etching a contact hole through the ILD layer and through a portion of the CESL, the contact hole exposing the CESL covering the sidewalls of the gate spacer and exposing a top portion of the S/D feature. The method includes forming a silicide feature on the S/D feature and selectively depositing an inhibitor on the silicide feature. The inhibitor is not deposited on surfaces of the CESL other than at a corner area where the CESL and the silicide feature meet.

Abstract: A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material.

Abstract: A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.

Abstract: A semiconductor device includes a metal gate structure having sidewall spacers disposed on sidewalls of the metal gate structure. In some embodiments, a top surface of the metal gate structure is recessed with respect to a top surface of the sidewall spacers. The semiconductor device may further include a metal cap layer disposed over and in contact with the metal gate structure, where a first width of a bottom portion of the metal cap layer is greater than a second width of a top portion of the metal cap layer. In some embodiments, the semiconductor device may further include a dielectric material disposed on either side of the metal cap layer, where the sidewall spacers and a portion of the metal gate structure are disposed beneath the dielectric material.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate and a gate electrode overlying the substrate. Further, the integrated chip includes a contact layer overlies the substrate and is laterally spaced apart from the gate electrode by a spacer structure. The spacer structure may surround outermost sidewalls of the gate electrode. A hard mask structure may be arranged over the gate electrode and between portions of the spacer structure. A contact via extends through the hard mask structure and contacts the gate electrode. The integrated chip may further include a liner layer that is arranged directly between the hard mask structure and the spacer structure, wherein the liner layer is spaced apart from the gate electrode.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.

Abstract: A method includes providing a structure having a substrate, gate stacks and source/drain (S/D) features over the substrate, S/D contacts over the S/D features, one or more dielectric layers over the gate stacks and the S/D contacts, and a via structure penetrating the one or more dielectric layers and electrically connecting to one of the gate stacks and the S/D contacts. The method further includes forming a ferroelectric (FE) stack over the structure, wherein the FE stack includes an FE layer and a top electrode layer over the FE layer, wherein the FE stack directly contacts the via structure; and patterning the FE stack, resulting in a patterned FE stack including a patterned FE feature and a patterned top electrode over the patterned FE feature.

Abstract: A method includes providing a structure having a substrate, a gate, a gate spacer, a dielectric gate cap, a source/drain (S/D) feature, a contact etch stop layer (CESL) covering a sidewall of the gate spacer and a top surface of the S/D feature, and an inter-level dielectric (ILD) layer. The method includes etching a contact hole through the ILD layer and through a portion of the CESL, the contact hole exposing the CESL covering the sidewalls of the gate spacer and exposing a top portion of the S/D feature. The method includes forming a silicide feature on the S/D feature and selectively depositing an inhibitor on the silicide feature. The inhibitor is not deposited on surfaces of the CESL other than at a corner area where the CESL and the silicide feature meet.