Patents by Inventor Lin Yu

Lin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230121408
    Abstract: A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20230119732
    Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Lin-Yu Huang, Li-Shen Yu, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11630582
    Abstract: A storage system and an access control method thereof are provided. The storage system receives a first I/O request from at least one hypervisor. The first I/O request is used for accessing a first disk file of disk files. The storage system then operates a first I/O operation of a first virtual disk of virtual disks according to the first I/O request since the disk files correspond to the virtual disks. The storage system reads a QoS data of the first disk file and determines a first delay period according to the QoS data. The storage system transmits a first I/O response to the at least one hypervisor after the first delay period.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: April 18, 2023
    Assignee: Silicon Motion Technology (Hong Kong) Limited
    Inventors: Kuan-Kai Chiu, Tsung-Lin Yu
  • Publication number: 20230104509
    Abstract: Direct memory access data path for RAID storage is disclosed, including: receiving, at a Redundant Array of Independent Disks (RAID) controller, a request to write data to be distributed among a plurality of storage devices; computing parity information based at least in part on the data associated with the request; causing the parity information to be stored on a first subset of the plurality of storage devices; and causing the data associated with the request to be stored on a second subset of the plurality of storage devices, wherein the plurality of storage devices is configured to obtain the data associated with the request directly from a memory that is remote to the RAID controller, and wherein the data associated with the request does not pass through the RAID controller.
    Type: Application
    Filed: September 27, 2021
    Publication date: April 6, 2023
    Inventors: Guo-Fu Tseng, Tsung-Lin Yu, Cheng-Yue Chang
  • Patent number: 11621649
    Abstract: A phase sequence adjustment system includes a power conversion circuit and a control circuit. The power conversion circuit is connected to a main power supply with a phase sequence. The control circuit respectively provides a first and a second excitation signals to the power conversion circuit, so as to short the power conversion circuit with the main power supply twice. The control circuit includes a current detection circuit and a control unit. The current detection circuit obtains two current signals respectively during two short-circuit operations. The control unit calculates two current phase angles respectively according to these two current signals and determines whether the phase sequence is positive or negative accordingly. The control unit selects one from the two current phase angles, calculates a voltage phase angle of the main power and a phase angle difference there-between to adjust a feedback phase sequence accordingly.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: April 4, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Lin-Yu Lu, Ming-Tsung Chen
  • Publication number: 20230102146
    Abstract: The present invention relates to a multi-target tyrosine kinase inhibitor, which is a compound having protein kinase inhibitory activity as shown in formula (I). The compound is metabolized into an active small molecule td32-4 that inhibits tumor growth in vivo, so as to achieve the anti-tumor effect. Compared with td32-4, the compound of the present invention has significantly improved solubility and oral bioavailability, and shows strong anti-tumor activity in animal in vivo experiments. The present invention relates to a synthetic method for the compound of formula (I) and an application thereof in the field of pharmaceuticals.
    Type: Application
    Filed: February 2, 2021
    Publication date: March 30, 2023
    Inventors: Shenglin LUAN, Tian TANG, Hanmin HUANG, Jing WU, Yidong FENG, Tao SHI, Hanlin FENG, Lin YU
  • Publication number: 20230075343
    Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 9, 2023
    Inventors: Li-Zhen YU, Huan-Chieh SU, Shih-Chuan CHIU, Lin-Yu HUANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20230061158
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 2, 2023
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20230066705
    Abstract: Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Sheng-Tsung WANG, Chia-Hao CHANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20230067799
    Abstract: Methods and devices that provide for a fin structure and a dielectric fin structure. A gate structure is formed over the fin structure and the hybrid fin structure. A plurality of dielectric layers is adjacent the gate structure and over the hybrid fin structure between the gate structure and a contact element over the dielectric fin structure. The plurality of dielectric layers includes an air gap, formed by removal of a dummy spacer layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Chia-Hao CHANG, Lin-Yu HUANG, Sheng-Tsung WANG, Cheng-Chi CHUANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Patent number: 11594602
    Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20230053595
    Abstract: A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Sheng-Tsung WANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Sung-Li WANG, Chih-Hao WANG
  • Patent number: 11588050
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes an epitaxial source feature and an epitaxial drain feature, a vertical stack of channel members disposed over a backside dielectric layer, the vertical stack of channel members extending between the epitaxial source feature and the epitaxial drain feature along a direction, a gate structure wrapping around each of the vertical stack of channel members, and a backside source contact disposed in the backside dielectric layer. The backside source contact includes a top portion adjacent the epitaxial source feature and a bottom portion away from the epitaxial source feature. The top portion and the bottom portion includes a step width change along the direction.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20230050249
    Abstract: A semiconductor device includes a first gate structure and a second gate structure over a fin, a dielectric cut pattern sandwiched by the first and second gate structures, and a liner layer surrounding the dielectric cut pattern. The dielectric cut pattern is spaced apart from the fin and extends further from the substrate than a first gate electrode of the first gate structure and a second gate electrode of the second gate structure. The semiconductor device further includes a conductive feature sandwiched by the first and second gate structures. The conductive feature is divided by the conductive feature into a first segment and a second segment. The first segment of the conductive feature is above a source/drain region of the fin.
    Type: Application
    Filed: April 26, 2022
    Publication date: February 16, 2023
    Inventors: Lin-Yu HUANG, Li-Zhen Yu, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20230034360
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate stack wrapping around first nanostructures, a second gate stack wrapping around second nanostructures, a gate isolation structure interposing between the first gate stack and the second gate stack, a first source/drain feature adjoining the first nanostructures, a second source/drain feature adjoining the second nanostructures, and a source/drain spacer structure interposing between the first source/drain feature and the second source/drain feature. The gate isolation structure covers a sidewall of the source/drain spacer structure.
    Type: Application
    Filed: February 15, 2022
    Publication date: February 2, 2023
    Inventors: Huan-Chieh Su, Zhi-Chang Lin, Li-Zhen Yu, Chun-Yuan Chen, Lo-Heng Chang, Cheng-Chi Chuang, Chih-Hao Wang, Lin-Yu Huang
  • Publication number: 20230036693
    Abstract: Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.
    Type: Application
    Filed: February 18, 2022
    Publication date: February 2, 2023
    Inventors: Kan-Ju Lin, Chien Chang, Chih-Shiun Chou, Tai Min Chang, Yi-Ning Tai, Hung-Yi Huang, Chih-Wei Chang, Ming-Hsing Tsai, Lin-Yu Huang
  • Publication number: 20230029002
    Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.
    Type: Application
    Filed: January 18, 2022
    Publication date: January 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chin Chang, Lin-Yu Huang, Shuen-Shin Liang, Sheng-Tsung Wang, Cheng-Chi Chuang, Chia-Hung Chu, Tzu Pei Chen, Yuting Cheng, Sung-Li Wang
  • Patent number: 11561871
    Abstract: A data transmission and protection system includes a plurality of solid-state drives (SSDs), a storage medium, a central processing unit (CPU) and a massively parallel processor (MPP). The storage medium storing an application program and a redundant array of independent disks (RAID) configuration. The CPU is coupled to the storage medium and configured to execute the application program to generate a virtual SSD interface for the plurality of SSDs according to the RAID configuration. The MPP is coupled to the virtual SSD interface and the plurality of SSDs. The MPP is configured to execute data exchange with the plurality of SSDs in response to a command received from the virtual SSD interface.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: January 24, 2023
    Assignee: GRAID Technology Inc.
    Inventors: Tsung-Lin Yu, Cheng-Yue Chang, Guo-Fu Tseng
  • Patent number: 11563001
    Abstract: A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: January 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu Huang, Chiao-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: D982595
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: April 4, 2023
    Assignee: The Procter & Gamble Company
    Inventors: Naoki Miyamoto, Lin Yu, Youn Joung Park, Yasuharu Shirai