Abstract: This invention discloses a probe card assembly with adjustable ZIF connectors. The probe card assembly comprises a substrate, a plurality of ZIF connectors and a plurality of adjustable fastening means for assembling and disassembling the ZIF connectors on the substrate. The substrate is a disc-like plate, having a first surface, a second surface, a plurality of concave sections disposed on the second surface and a plurality of first through holes perpendicular to the first surface. The first through holes are circularly arranged toward the substrate center. Pairs of first contacts are provided on the first surface adjacent to both sides of first through holes. A plurality of terminals are protruded from the second surface of the substrate for contacting and testing the wafer. The ZIF connectors are also circularly arranged toward the substrate center.

Abstract: This invention discloses a test board with detachably adjustable ZIF connectors. The test board comprises a test substrate, a plurality of ZIF connectors and a plurality of detachably adjustable fastening means for assembling and disassembling the ZIF connectors on the test substrate. The test substrate has a first surface, a second surface and a plurality of first through-holes perpendicular to the first surface. Pairs of first electrical pads are provided on the first surface adjacent to both sides of first through-holes. A plurality of second electrical pads are provided on the second surface of the test substrate for electrically connecting the first electrical pads. The ZIF connectors are arranged on the first surface of the substrate. Each ZIF connector has a plurality of parallel second through-holes arranged from the top to the bottom of the connector and pairs of electrical terminals are disposed on the bottom of each ZIF connector for contacting the first electrical pads of the test substrate.

Abstract: Devices and methods for DC and SLT (system level test) integration are disclosed. The DC circuit and the SLT circuit are integrated into the same device. Therefore, the DUT (device under testing) can precede the SLT before the FT (final test) when the DUT passes the DC.