Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: A system may include one or more processors, a memory in communication with the one or more processors, and storing instructions, that when executed by the one or more processors, are configured to cause the system to predict user travel. The system may receive transaction data, and extract travel information from the transaction data. The system may assign a confidence score to the travel information based on comparing the travel information to previous travel information. The system may determine whether the confidence score is greater than or equal to one or more thresholds. Responsive to determining the confidence score is greater than or equal to one or more thresholds, the system may perform one or more fraud prevention activities.

Abstract: Packets are routed in a data network comprising a wireless mesh network and a controller providing IPv6 management traffic to nodes of the wireless network. A monitor function and a route table manager are used to generate a route table relating IPv6 addresses to each of the nodes via a respective one of a plurality of POP nodes, by accessing a pre-configured topology file, determining the reachability of each of the plurality of POP nodes from the controller by periodically sending test messages from the monitor function to each POP and detecting acknowledgement of the test messages. If a POP node is not reachable, the route table is updated to relate the IPv6 subnet of the POP that is not reachable to the address of a POP node that is reachable. A Layer 2 network is used to direct the IPv6 management traffic according to the amended route table.

Abstract: A system and method for providing avatar device status indicators for voice assistants in multi-zone vehicles. The method comprises: receiving at least one signal from a plurality of microphones, wherein each microphone is associated with one of a plurality of spatial zones, and one of a plurality of avatar devices; wherein the at least one signal further comprises a speech signal component from a speaker; wherein the speech signal component is a voice command or question; sending zone information associated with the speaker and with one of the plurality of spatial zones to an avatar; activating one the plurality of avatar devices in a respective one of the plurality of spatial zones associated with the speaker.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.

Abstract: A disclosed high-density capacitor includes a top electrode having an electrically conducting material forming a three-dimensional structure. The three-dimensional structure includes a plurality of vertical portions extending in a vertical direction and horizontal portions, that are interleaved within the vertical portions and extend in a first horizontal direction. The high-density capacitor further includes a dielectric layer formed over the top electrode, and a bottom electrode including an electrically conducting material, such that the bottom electrode is separated from the top electrode by the dielectric layer. Further, the bottom electrode envelopes some of the plurality of vertical portions of the top electrode. The disclosed high-density capacitor further includes a plurality of support structures that are aligned with the first horizontal direction such that the horizontal portions of the top electrode are formed under respective support structures.

Abstract: An image processing method applied to a display device having a processing circuit and a screen and includes: receiving a first image from one of a plurality of electronic devices; detecting whether the first image has a black border area; and if the first image has the black border area, performing a first display operation, wherein performing the first display operation includes: removing the black border area of the first image, to generate a second image; adjusting the size of the second image according to the size of a display area of the screen; calculating a first blank area of the screen based on the adjusted second image; requesting a third image from another one of the electronic devices according to the size of the first blank area; and filling the display area of the screen with the adjusted second image and the third image.

Abstract: A resistance hinge includes a first hinge bracket, a fixing shaft fastened in the first hinge bracket, a locating holder surrounding the fixing shaft, a friction part, a second hinge bracket and a transmission module. The friction part is formed in a hollow cylinder shape and surrounds the locating holder together with the fixing shaft. The second hinge bracket is pivotally mounted on the first hinge bracket. The transmission module is connected between the friction part and the second hinge bracket.

Abstract: A boot method for an embedded system is provided. The embedded system includes two mainboards each provided with a baseboard management controller (BMC), a non-volatile memory unit and a network adapter. When the embedded system is turned on, each of the BMCs performs a boot procedure, and then loads an operating system (OS) image file from a corresponding non-volatile memory unit to execute an operating system. When one BMC fails to load the OS image file or to execute the operating system, the BMC causes the corresponding network adapter to communicate with the other network adapter to acquire the OS image file from, the non-volatile memory unit on the other mainboard, so as to replace the OS image file in the corresponding non-volatile memory unit, and directly loads the OS image thus acquired to execute the operating system.

Abstract: A semiconductor structure includes two circuit regions and two inner seal rings, each of which surrounds one of the circuit regions. Each inner seal ring has a substantially rectangular periphery with four interior corner stress relief (CSR) structures. The semiconductor structure further includes an outer seal ring surrounding the two inner seal rings. The outer seal ring has a substantially rectangular periphery without CSR structures at four interior corners of the outer seal ring. The outer seal ring includes a plurality of first fin structures located between each of the two inner seal rings and a respective short side of the outer seal ring. Each first fin structure is parallel with the respective short side of the outer seal ring. Lengths of the first fin structures gradually decrease along a direction from the inner seal rings to the respective short side of the outer seal ring.

Abstract: A development system and a method of an offline software-in-the-loop simulation are disclosed. A common firmware architecture generates a chip control program. The common firmware architecture has an application layer and a hardware abstraction layer. The application layer has a configuration header file and a product program. A processing program required by a peripheral module is added to the hardware abstraction layer during compiling. The chip control program is provided to a controller chip or a circuit simulation software to be executed to control the product-related circuit through controlling the peripheral module.

Abstract: A semiconductor device includes a semiconductor stack, a third semiconductor structure, a dielectric layer, and a reflective layer under the third semiconductor structure. The semiconductor stack includes a first semiconductor structure, an active structure, a second semiconductor structure. The first semiconductor structure has a first surface which includes a first portion and a second portion, and the first surface has a first area. The third semiconductor structure connects to the first portion, and has a second surface with a second area. The dielectric layer connects to the second portion and includes a plurality of openings, and the plurality of openings have a third area. A ratio of the second area to the first area is between 0.1˜0.7, and a ratio of the third area to the first area is less than 0.2.

Abstract: The present invention relates to a conjugate of a cytotoxic drug/molecule to a cell-binding molecule with a bis-linker (a dual-linker) containing a 2,3-diaminosuccinyl group. It also relates to preparation of the conjugate of a cytotoxic drug/molecule to a cell-binding molecule with the bis-linker, particularly when the drug having functional groups of amino, hydroxyl, diamino, amino-hydroxyl, dihydroxyl, carboxyl, hydrazine, aldehyde and thiol for conjugation with the bis-linker in a specific manner, as well as the therapeutic use of the conjugates.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.

Abstract: A lighting apparatus includes a bridge circuit, a current source, a first LED module, a second LED module and a switch. The bridge circuit is used for rectifying an input AC power to generate a DC power. The current source receives the DC power to generate a driving current. The first LED module emits a first light of a first color temperature. The second LED module emits a second light of a second color temperature. The switch is coupled to the current source to change at least a resistance parameter corresponding to a current ratio between the first LED module and the second LED module to generate a mixed light of a mixed color temperature.

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes an interposer substrate over the wiring substrate. The interposer substrate includes a redistribution structure, a dielectric layer, a conductive via, and a plurality of first dummy vias, the dielectric layer is over the redistribution structure, the conductive via and the first dummy vias pass through the dielectric layer, the first dummy vias surround the conductive via, and the first dummy vias are electrically insulated from the wiring substrate. The chip package structure includes a chip structure over the interposer substrate. The chip structure is electrically connected to the conductive via, and the chip structure is electrically insulated from the first dummy vias.

Abstract: An antenna module includes a first antenna layer, including at least one main radiation unit including at least two main radiation patches symmetrically arranged and spaced apart from each other and at least one feeder portion located at or corresponds to a gap between adjacent two of the main radiation patches; a second antenna layer, stacked with the first antenna layer and including a reference ground arranged opposite to the main radiation patches and at least one microstrip insulated from the reference ground; at least one first electrically conductive member, electrically connected to the main radiation patches and the reference ground; and at least one second electrically conductive member, with an end being electrically connected to the feeder portion and another end being electrically connected to another end of the microstrip. An end of the microstrip is electrically connected to a radio frequency transceiver chip.