Abstract: The invention relates to a decorative surface covering element, in particular a floor panel, ceiling panel or wall panel. The invention also relates to a panel covering, such as a floor covering, ceiling covering or wall covering, comprising a plurality of panels according to the invention. The invention further relates to a method of producing a decorative surface covering element according to the invention.

Abstract: An integrated substrate for an anti-shake apparatus defined with an optical axis includes: a substrate, a lens module, an anti-shake apparatus and an image-sensing module. The substrate includes a frame having, a predetermined thickness. The frame includes a first surface, a second surface, a first circuit layout, and a second circuit layout. The lens module is located above the substrate on the optical axis. The anti-shake apparatus is furnished between the lens module and the substrate. The image-sensing module has an active side and an inactive side, and the inactive side is furnished onto the second surface. The active side is located on the optical axis in a manner of facing the lens module. The anti-shake apparatus is coupled to the first circuit layout, while the image-sensing module is coupled to the second circuit layout. The first and second circuit layouts comprise a plurality of first and second metal leads, respectively.

Abstract: A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.

Abstract: The present disclosure provides a protection casing assembly for a wearable device. The protection casing assembly includes a main case and a frame. The main case has a first accommodation space and configured to allow a wearable device to be disposed detachably. When the wearable device is disposed in the first accommodation space, the wearable device and the main case define a second accommodation space adjacent to at a device surface of the wearable device. The frame is detachably disposed in the second accommodation space.

Abstract: A cybersecurity system, method, and computer program is provided for detecting whether an entity's collection of processes during an interval is abnormal compared to the historical collection of processes observed for the entity during previous intervals of the same length. Logs from a training period are used to calculate global and local risk probabilities for each process based on the process's execution history during the training period. Risk probabilities may be computed using a Bayesian framework. For each entity in a network, an entity risk score is calculated by summing the applicable risk probabilities of the unique processes executed by the entity during an interval. An entity's historical risk scores form a score distribution. If an entity's current score is an outlier on the historical score distribution, an alert of potentially malicious behavior is generated with respect to the entity. Additional post-processing may be performed to reduce false positives.

Abstract: A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.

Abstract: An integrated chip includes a substrate, an isolation structure and a poly gate structure. The isolation structure includes dielectric materials within the substrate and having sidewalls defining an active region. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source region has a first width along a second direction perpendicular to the first direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and larger than the first and second widths. The poly gate structure extends over the channel region. The poly gate structure includes a first doped region having a first type of dopants and a second doped region having a second type of dopants. The second type is different from the first type.

Abstract: A fluorine-free composition includes at least one polycarbodiimide compound derived from a carbodiimidization reaction of a carbodiimidization reaction mixture comprising at least one oligomer, wherein the oligomer comprises at least one isocyanate end group and at least two repeating units, wherein each of the at least two repeating units comprises at least one hydrocarbon group having at least 16 carbon atoms. The composition may also include at least one paraffin wax. Such compositions are useful for treating fibrous substrates to enhance their water-repellency.

Abstract: A connector structure is provided, including an insulating body, a plurality of terminals disposed in the insulating body, at least one stopper, and a housing receiving the insulating body and the terminals. A portion of the insulating body is abutted between the housing and the at least one stopper, and contacting portions of the housing and the at least one stopper are structurally combined together.

Abstract: Provided is a graphene foam-based sealing material comprising: (a) a graphene foam framework comprising pores and pore walls, wherein the pore walls comprise a 3D network of interconnected graphene planes or graphene sheets; and (b) a permeation-resistant binder or matrix material that coats and embraces the exterior surfaces of the graphene foam framework and/or infiltrates into pores of the graphene foam, occupying from 10% to 100% (preferably from 10% to 98% and more preferably from 20% to 90%) of the pore volume of the graphene foam framework.

Abstract: A woven textile defines a longitudinal direction and a transverse direction and includes a first layer, a second layer, and at least one binding thread. The first layer includes at least one first braid extending in a sinusoidal wave pattern. The second layer includes a plurality of rows of second braid extending along the transverse direction in a sinusoidal wave pattern. The rows of second braid are aligned along the longitudinal direction and are separated. Each of the rows of second braid is stacked with the at least one first braid to form a plurality of overlap portions. The at least one binding thread is woven with each of the rows of second braid and the at least one first braid together at the overlap portions to fix the row of second braid and the at least one first braid.

Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.

Abstract: An attraction system includes a sensor configured to emit an output signal toward a guest area and receive a reflected signal from the guest area and a control system communicatively coupled to the sensor. The control system is configured to receive data from the sensor, in which the data is indicative of a distance of signal travel based on the output signal and the reflected signal. The control system is also configured to compare the distance of signal travel with an unoccupied distance value corresponding to a distance between the sensor and the guest area being unoccupied, and determine whether the guest area is occupied based on comparing a difference between the distance of signal travel and the unoccupied distance value with a threshold.

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and a control module, electrically connected to the amplification module; wherein, in an offset compensation stage of the sense amplifier, the control module is used to configure the amplification module to comprise a diode structure, a current mirror structure, and an inverter with an input and an output connected together; and in a first amplification stage of the sense amplifier, the control module is used to configure the amplification module as an inverter. The present disclosure can realize the offset compensation of the sense amplifier, thereby improving the performance of semiconductor memories.

Abstract: Configuration of a communication module based on determination of an idle time metric is described. In one embodiment, signal strength data representative of composite signal strength indicators of a group of frequency channels utilized by the communication module is determined. A composite indicator of the composite signal strength indicators can be employed that comprises multiple signal strength indicators, sampled over time, of a first channel of the group of frequency channels. Respective values for the composite indicator can be assigned in response to comparisons of the multiple signal strength indicators to one or more defined threshold(s). An idle time metric of the first channel can be determined based on a combination of the respective values and a best channel from among the group of frequency channels can be determined based on the idle time metric. The communication module can be updated to communicate via the best channel.