Abstract: A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

Abstract: A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

Abstract: A control method applied to an electronic device with a first screen and a second screen is provided. The control method includes the following steps: receiving touch data responding to a touch behavior generated by the second screen; determining whether the touch behavior is a touchpad operation instruction or a touch screen operation instruction according to the touch data; triggering corresponding touchpad operation according to the touch data when the touch behavior is the touchpad operation instruction; and triggering corresponding touch screen operation according to the touch data when the touch behavior is the touch screen operation instruction.

Abstract: Disclosed is a simulation design method for bay layer devices of a smart substation. Application layer modules of two network structures store identity tags of each other's application layer modules respectively, so that a simulation model of the bay layer devices has ports of both network structures and can realize data sharing. The simulation model of the bay layer devices can process SV messages, GOOSE messages and MMS messages simultaneously. An interface layer is additionally configured between an application layer and a data link layer to allow data to be directly mapped to the data link layer from the application layer, so that received or transmitted messages contain actual electrical quantity information. The invention provides model establishment methods of two network structures, thus not only suitable for simulation of the bay layer devices, but also suitable for simulation of station control layer devices and process layer devices.

Abstract: Organic light emitting materials and devices comprising phosphorescent metal complexes comprising ligands comprising aryl or heteroaryl groups substituted at both ortho positions are described. An organic light emitting device, comprising: an anode, a hole transport layer; an organic emissive layer comprising an emissive layer host and an emissive dopant; an electron impeding layer; and electron transport layer; and a cathode disposed, in that order, over a substrate.

Abstract: A method includes providing a structure having a substrate, gate stacks and source/drain (S/D) features over the substrate, S/D contacts over the S/D features, one or more dielectric layers over the gate stacks and the S/D contacts, and a via structure penetrating the one or more dielectric layers and electrically connecting to one of the gate stacks and the S/D contacts. The method further includes forming a ferroelectric (FE) stack over the structure, wherein the FE stack includes an FE layer and a top electrode layer over the FE layer, wherein the FE stack directly contacts the via structure; and patterning the FE stack, resulting in a patterned FE stack including a patterned FE feature and a patterned top electrode over the patterned FE feature.

Abstract: A pre-treatment composition comprising water, reactive crosslinking agents and polyurethane particles polyurethane particles including sulfonated- or carboxylated-diamine groups, isocyanate-generated amine groups, and polyalkylene oxide side-chains. Also disclosed is a pre-treated printable medium comprising a base substrate and the pre-treatment composition, such as described herein, that is applied over, at least, one side of the base substrate, forming an image-receiving surface. Also disclosed is the method for making such printable medium.

Abstract: An object display method is provided for a terminal. The method includes displaying a first object in an object display region in a game interface and, after detecting a first operation performed on the first object, displaying a second object in the game interface in response to the first operation. The first object is used for controlling, in response to a second operation performed on the first object, a game character to perform a first target operation, and the second object is used for controlling, in response to a third operation performed on the second object, the game character to perform a second target operation.

Abstract: An information handling system includes a cooling fan operable in one of a plurality of fan speed levels, and a connector to which a headphone device can be connected. A mode controller sets the cooling fan to a first fan speed levels, receives an indication that the headphone device is connected to the connector, and sets the cooling fan in a second, higher fan speed level in response to receiving the indication.

Abstract: To enable efficient uplink transmission. A terminal apparatus includes: a coder configured to code a UCI payload and perform rate matching of coded bits of the UCI payload; and a transmitter configured to transmit the UCI payload by using a PUSCH, the UCI payload includes at least HARQ-ACK information and/or CSI, a length of an output sequence EUCI of the rate matching is provided based on a first number of CRC bits LUCI, the first number of CRC bits LUCI is provided based on a size of the payload, and a size of second CRC bits added to the payload is provided based on the size of the payload and the length of the output sequence EUCI of the rate matching.

Abstract: An array substrate, a display panel, a display device, and a manufacturing method for an array substrate are provided. The array substrate includes a pixel unit group which includes a first pixel and a second pixel; the first pixel includes a first pixel electrode, a first switching element, and a first connection portion extending and protruding from the first pixel electrode; the second pixel includes a second pixel electrode, a second switching element, and a second connection portion extending and protruding from the second pixel electrode; the first pixel electrode and the first switching element are electrically connected to each other via the first connection portion; the second pixel electrode and the second switching element are electrically connected to each other via the second connection portion; and an extension length of the first connection portion is not equal to an extension length of the second connection portion.

Abstract: An OLED touch and display driver integration chip is provided, including: at least one group of display driving pads for providing display driving signals to the OLED touch display panel; at least one group of touch pads for providing touch driving signals to touch electrodes on the OLED touch display panel, and alternately arranged in groups with the at least one group of display driving pads; at least one group of isolation pads, each group of isolation pads includes at least one isolation pad and is arranged between a group of display driving pads and a group of touch pads that are adjacent, an isolation pad is configured to apply a specific signal to isolate signal interference between adjacent groups of display driving pads and touch pads, or configured to apply a specific signal or be in a floating state, to reduce load of data lines or the touch electrodes.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.

Abstract: The present disclosure describes a sidelink communication method and a terminal device. The method includes transmitting, by a second terminal device, sidelink control information (SCI) to a first terminal device. The SCI is used by the first terminal device to obtain information of a sidelink reference signal, and includes a first indication field used for indicating the first terminal device to determine resource indication information of the sidelink reference signal. In response to the resource indication information of the sidelink reference signal including frequency domain start position indication information of the sidelink reference signal but not frequency domain length information of the sidelink reference signal, the frequency domain length information of the sidelink reference signal is determined based on pre-configured information or information configured by a network device.

Abstract: An organic light-emitting diode (OLED) display panel and a manufacturing method thereof are provided. An organic material and an inorganic nano-particle material are placed in a crucible under a high-pressure gas after vacuuming, the inorganic nanoparticles and the organic material are highly uniformly mixed during an evaporation process, and an encapsulation layer is formed integrally into one piece by adjusting an evaporation rate ratio of the organic material to the inorganic nano-particle material. The film layer stability and transmittance are optimized, and the inorganic nanoparticles are uniformly distributed, thereby improving the light transmittance of the OLED display panel.

Abstract: A traffic condition prediction system and a traffic condition prediction method are disclosed. The method includes: determining a center of circle in a surveillance image of a target traffic scene; determining a first circle based on the center of circle and a first radius; extracting a plurality of first feature points along the circumference of the first circle according to a first preset sampling frequency; generating a scene feature of the target traffic scene at least based on the first feature points; determining whether the scene feature and a scene feature of another traffic scene are similar; and when determining that they are similar, predicting traffic condition of the target traffic scene through a prediction model used for predicting traffic condition of the other traffic scene. The scene feature of the target traffic scene and that of the other traffic scene are generated in a same way.

Abstract: A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.

Abstract: A device includes a first plurality of conductive strips have lengthwise directions in a first direction, a selector array overlapping the first plurality of conductive strips, an electrode array overlapping the selector array, a plurality of memory strips over the electrode array, and a second plurality of conductive strips overlapping the plurality of memory strips. The plurality of memory strips and the second plurality of conductive strips have lengthwise directions in a second direction perpendicular to the first direction.

Abstract: The present invention provides a control method of multiple memory devices, wherein the multiple devices comprise a first memory device and a second memory device, and the control method includes the steps of: determining a first operation timing and a second operation timing according to at least a first command signal that a first memory controller needs to send to the first memory device; controlling the first memory controller to send the first command signal to the first memory device at the first operation timing; and controlling the second memory controller to send the second command signal to the second memory device at the second operation timing.