Abstract: Systems, devices, and methods for managing conductive connections for semiconductor devices are provided. In one aspect, a method includes: providing an integrated structure including an array structure in a first region and a conductive connection structure in a second region adjacent to the first region, at least one portion of at least one polysilicon layer being over the conductive connection structure; etching the at least one portion of the at least one polysilicon layer to expose one or more conductive connections in the conductive connection structure; depositing an isolating material over the array structure and the conductive connection structure; and forming conductive vertical interconnect accesses (VIAs) through the isolating material to be in contact with the one or more conductive connections and a conductive layer in the array structure.

Abstract: The present disclosure provides a semiconductor device and a preparation method thereof. The semiconductor device includes a body structure and an outer edge structure at a periphery of a bottom of the body structure. The body structure includes a top surface and a bottom surface arranged opposite to each other, and a side surface between the top surface and the outer edge structure. The side surface includes a first side surface connected with the outer edge structure, and a lateral distance of the first side surface relative to the outer edge structure gradually decreases along a direction from the top surface to the bottom surface.

Abstract: A method includes forming storage channel structures including a functional layer, a channel layer, a filling layer and a slit in the filling layer, thinning a first substrate to form a second substrate, removing a second bottom section outside the second substrate to expose a first bottom section slit, filling a dielectric material layer in the first bottom section slit, removing the second substrate and a first bottom section functional layer to form a first dielectric section filled in the first bottom section slit and expose a first bottom section channel layer, forming a common source layer contacting the first bottom section channel layer, the first bottom section filling layer and the first dielectric section. After inverting the stack structure, the substrate is thinned, and the exposed functional layer and the channel layer are removed.

Abstract: A semiconductor device fabrication method includes providing a processing wafer. The processing wafer has core and staircase structure (SS) regions, and includes a bottom conductor layer, conductor/dielectric tier(s) over the bottom conductor layer, and a channel hole (CH) in the core region and extending approximately vertically through the conductor/dielectric tier(s). The CH includes a channel layer and a memory film surrounding the channel layer. A protrusion portion of the channel layer and a protrusion portion of the memory film extend into the bottom conductor layer. The method further includes patterning the bottom conductor layer to remove a portion of the bottom conductor layer in the core region to expose the protrusion portion of the memory film, performing etching to remove the protrusion portion of the memory film to expose the protrusion portion of the channel layer, performing impurity implantation, and performing laser activation.

Abstract: In certain aspects, a method for controlling wafer stress is disclosed. A semiconductor film is formed on a backside of a wafer. The wafer is deformed by stress associated with a front-side semiconductor structure on a front side of the wafer opposite to the backside of the wafer. A laser application region of the semiconductor film is determined. A laser anneal process is performed in the laser application region of the semiconductor film.

Abstract: In certain aspects, a method for controlling wafer stress is disclosed. A semiconductor film is formed on a backside of a wafer. The wafer is deformed by stress associated with a front-side semiconductor structure on a front side of the wafer opposite to the backside of the wafer. A laser application region of the semiconductor film is determined. A laser anneal process is performed in the laser application region of the semiconductor film.

Abstract: A semiconductor device includes a first die including a first stack of layers in a first region on a backside of the first die and a second stack of layers in a second region on the backside of the first die. The first stack of layers has a smaller number of different layers than the second stack of layers. A contact structure is formed in the first region on the backside of the first die. The contact structure extends through the first stack of layers and is configured to conductively connect a first conductive structure on a face side of the first die with a second conductive structure on the backside of the first die. The face side is opposite to the backside.