Abstract: A display substrate includes a base substrate including an aperture region, a transition region surrounding the aperture region and a display region surrounding the transition region, at least one annular isolation column structure located in the transition region, where the isolation column structure includes a plurality of isolation columns laminated sequentially in the direction away from the base substrate and an isolation layer located at one side of the isolation columns away from the base substrate, the isolation columns surrounding the aperture region, a recessed portion is formed in a side face of at least one isolation column, and a display layer covering the transition region and the display region, where the display layer includes a light-emitting layer, and the light-emitting layer is arranged in such a manner as to be interrupted by the recess of the isolation column.

Abstract: The present disclosure provides a thin film transistor, a manufacturing method of the thin film transistor and a display device, configured to improve electrical property of the thin film transistor. The thin film transistor includes: an active layer, including a source and drain contact region and a channel region; a metal barrier layer, covering the source and drain contact region; a first gate insulating layer, at least covering the channel region and exposing the metal barrier layer; a gate, on the first gate insulating layer and covering the channel region; an inner layer dielectric layer, on the gate and having a through hole exposing the metal barrier layer; and a source and drain, on the inner layer dielectric layer and in contact with the metal barrier layer through the through hole.

Abstract: The present disclosure provides a thin film transistor, a manufacturing method of the thin film transistor and a display device, configured to improve electrical property of the thin film transistor. The thin film transistor includes: an active layer, including a source and drain contact region and a channel region; a metal barrier layer, covering the source and drain contact region; a first gate insulating layer, at least covering the channel region and exposing the metal barrier layer; a gate, on the first gate insulating layer and covering the channel region; an inner layer dielectric layer, on the gate and having a through hole exposing the metal barrier layer; and a source and drain, on the inner layer dielectric layer and in contact with the metal barrier layer through the through hole.