Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack over a substrate, wherein the alternating dielectric stack includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack and extending into the substrate, wherein the channel structure includes a channel layer disposed on a sidewall of a memory film. The method further includes removing the substrate and a portion of the memory film that extends into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure.

Abstract: In an example, a three-dimensional (3D) memory device includes a stack structure including interleaved conductive layers and dielectric layers, a first semiconductor layer above the stack structure, a second semiconductor layer above the first semiconductor layer, channel structures extending vertically through the stack structure and the first semiconductor layer, and a source contact in contact with the second semiconductor layer.

Abstract: A semiconductor device includes a first dielectric layer, a source layer at a first side of the first dielectric layer and in contact with the first dielectric layer, a second dielectric layer at a second side opposite to the first side of the first dielectric layer and in contact with the first dielectric layer, a source contact structure extending vertically through the second dielectric layer and the first dielectric layer, and extending into the source layer and without penetrating through the source layer, a stack including interleaved stack conductive layers and stack third dielectric layers, the source layer being located between the first dielectric layer and the stack in a vertical direction, a channel structure extending vertically through the stack and the source layer, and an insulating structure extending vertically through the stack into the source layer.

Abstract: Methods, devices, and systems for three-dimensional (3D) memory devices are provided. In one aspect, a method for forming a three-dimensional (3D) semiconductor device includes: forming a first stack structure including a plurality of alternating sacrificial layers and dielectric layers, the first stack structure having a first region and a second region; forming gate line slits extending through the first stack structure in the first region and the second region; forming a contact via extending to a target sacrificial layer in the second region; forming cavities coupled to the contact via through the gate line slits; and forming conductive layers in replace of the sacrificial layers in the cavities and a contact in the contact via by depositing a conductive material in the contact via and the cavities. The 3D semiconductor device includes a second stack structure having the conductive layers and the dielectric layers.

Abstract: A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer, a spacer structure through the conductive layer and in contact with the insulating layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel, a portion of the semiconductor channel being in contact with the conductive layer. The contact structure includes a first contact portion and a second contact portion in contact with each other.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack comprising interleaved conductive layers and dielectric layers, a plurality of semiconductor layers contacted with each other and located adjacent to the memory stack, a plurality of channel structures each extending vertically through the memory stack and at least one of the semiconductor layers, a source contact in contact with at least one of the semiconductor layers, and a contact pad located on one side of the semiconductor layers that are away from the memory stack.

Abstract: A memory device can include channel structures in a first region. The memory device can also include a plurality of word line cavity structures in a second region abutting the first region. The plurality of word line cavity structures can extend along a first direction. Each of the word line cavity structures can include a first contact structure in a first side of the word line cavity structure along a second direction perpendicular to the first direction. Each of the word line cavity structures can also include a second contact structure in a second side of the word line cavity structure along the second direction. The second side can be opposite to the first side. Each of the word line cavity structures can further include a slit structure. The first contact structure and the second contact structure can be separated with the slit structure along the second direction.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a stop layer, a polysilicon layer, a memory stack including interleaved stack conductive layers and stack dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and the polysilicon layer, stopping at the stop layer.

Abstract: A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer and including a first conductive sublayer and a second conductive sublayer, a memory stack disposed on a side of the conductive layer away from the insulating layer, a spacer structure through the conductive layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel. The contact structure includes a first contact portion and a second contact portion in contact with each other. A lateral cross-sectional area of the second contact portion is greater than a lateral cross-sectional area of the first contact portion. A portion of the semiconductor channel is in contact with the first conductive sublayer. The second conductive sublayer is disposed between the first conductive sublayer and the memory stack.

Abstract: Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a method for forming a semiconductor device includes forming a spacer structure from a first surface of the base structure into the base structure, forming a first contact portion surrounded by the spacer structure, and forming a second contact portion in contact with the first contact portion. The second contact extends from a second surface of the base structure into the base structure.

Abstract: A 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel A first doping concentration of part of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of part of the semiconductor channel in the second portion of the channel structure.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes an insulating layer, a semiconductor layer, a memory stack including interleaved conductive layers and dielectric layers, a source contact structure extending vertically through the insulating layer from an opposite side of the insulating layer with respect to the semiconductor layer to be in contact with the semiconductor layer, and a channel structure extending vertically through the memory stack and the semiconductor layer into the insulating layer or the source contact structure.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a second region, and word lines each extending from the first region into at least a portion of the second region. At least one word line pick-up structure includes multiple sections each electrically connected to a different word line.

Abstract: A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole structure in the first region. The dummy channel hole structure is adjacent to the blocking structure, and includes a dielectric material that fills a channel hole to form a first dielectric filling structure.

Abstract: A 3D memory device includes a conductor/insulator stack, a channel hole structure extending through the conductor/insulator stack, and a staircase contact (SCT). The conductor/insulator stack includes a first conductive layer and a first dielectric layer alternatingly stacked. The SCT includes a conductive structure, extends through the first dielectric layer, contacts a second dielectric layer, and is electrically connected to the first conductive layer. The second dielectric layer is parallel to the first conductive layer.

Abstract: Aspects of the disclosure provide a semiconductor device including a stack structure and a first conductive pillar. The stack structure can include a plurality of interlayer insulating layers and gate layers arranged alternately along a stack direction, and stack structure an array region and a staircase region adjoining the array region. The stack structure has a plurality of staircases in the staircase region arranged corresponding to the gate layers. Each of the gate layers can include a first gate part at the corresponding staircase and a second gate part connected to the first gate part, and a thickness of the first gate part along the stack direction is less than that of the second gate part along the stack direction. The first conductive pillar is arranged in the staircase region and penetrates through the stack structure along the stack direction, and the first conductive pillar is electrically connected with the first gate part.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of conductive layers and insulating layers stacked alternatingly in a first direction. The stack of conductive layers and insulating layers has a first side and a second side in the first direction. The semiconductor device then includes a semiconductor layer at the first side of the stack of conductive layers and insulating layers, and a first isolation structure extending through, in the first direction, the semiconductor layer and a subset of the stack of conductive layers and insulating layers. The subset of the stack of conductive layers and insulating layers includes a first conductive layer. The first isolation structure separates a first portion of the first conductive layer from a second portion of the first conductive layer.

Abstract: A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, and a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The semiconductor channel includes an angled structure, and a first width of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second width of the semiconductor channel at an upper portion of the channel structure above the angled structure.

Abstract: A memory device includes a stack structure, channel structures, and a slit structure. The stack structure includes interleaved conductive layers and dielectric layers, and the conductive layers include a plurality of word lines. Each of the channel structures extends vertically through the stack structure. The slit structure extends vertically through the stack structure. An outer region of the stack structure includes a staircase structure, and the interleaved conductive layers and dielectric layers in a bottom portion of the stack structure are wider than the interleaved conductive layers and dielectric layers in a top portion of the stack structure. A first outer width of the slit structure in the bottom portion of the stack structure is greater than a second outer width of the slit structure in the top portion of the stack structure.