Patents by Inventor Linck Cheng

Linck Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for performing memory repair analysis
    Patent number: 6751760
    Abstract: A method and a system for performing memory repair analysis are provided. A merge circuit is connected between test storage device of semiconductor testing equipment and pre-analysis storage device of repair analysis apparatus. Prior to memory repair analysis process, data from a plurality of functional tests are merged as a functional test data with addresses of fail bits by the merge circuit, then stored in pre-analysis storage device for analyzing. Therefore, test time is reduced and test efficiency is improved.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: June 15, 2004
    Assignee: ChipMOS Technologies Inc.
    Inventors: Yuan-Ping Tseng, Vincent Wang, Linck Cheng, An-Hong Liu
  • System and method for avoiding waiting repair analysis for semiconductor testing equipment
    Publication number: 20030101388
    Abstract: A system and a method for avoiding waiting repair analysis for a semiconductor testing equipment are disclosed. The semiconductor testing equipment directly executes next functional test after transferring previous test data regardless of if repair analysis is completed or not. A repair analysis apparatus has a pre-analysis storage device with a larger capacity than the test storage device of the semiconductor testing equipment for off-line repair analysis, so that the semiconductor test is efficiently improved.
    Type: Application
    Filed: November 28, 2001
    Publication date: May 29, 2003
    Applicant: ChipMOS TECHNOLOGIES INC.
    Inventors: Yuan-Ping Tseng, Vincent Wang, Linck Cheng, An-Hong Liu
  • Method and system for performing memory repair analysis
    Publication number: 20030097626
    Abstract: A method and a system for performing memory repair analysis are provided. A merge circuit is connected between test storage device of semiconductor testing equipment and pre-analysis storage device of repair analysis apparatus. Prior to memory repair analysis process, data from a plurality of functional tests are merged as a functional test data with addresses of fail bits by the merge circuit, then stored in pre-analysis storage device for analyzing. Therefore, test time is reduced and test efficiency is improved.
    Type: Application
    Filed: November 20, 2001
    Publication date: May 22, 2003
    Applicant: chipMOS TECHNOLOGIES INC.
    Inventors: Yuan-Ping Tseng, Vincent Wang, Linck Cheng, An-Hong Liu