Patents by Inventor Lincoln J. Lauhon

Lincoln J. Lauhon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11705373
    Abstract: A system and method for performing in-situ measurements of semiconductor devices during chemical vapor deposition (CVD) includes disposing a chip carrier within a sealed chamber of a reactor for carrying out in-situ monitoring of partially fabricated semiconductor devices. The chip carrier includes a plurality of metallized bonding pads disposed along both peripheral edges on a same surface of the base for making electrical connections to metallized pads or contacts on the semiconductor device through bonding wires. Each of the plurality of metallized bonding pads disposed along both peripheral edges is electrically connected to each other as a pair through electrically connecting to a corresponding pair of ports which are disposed along both peripheral edges of the chip carrier. In-situ monitoring of the partially fabricated semiconductor device is performed through connecting the plurality of ports on the chip carrier to an external source-measure unit through a connector and wire harness.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: July 18, 2023
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Michael J. Moody, Lincoln J. Lauhon, Ju Ying Shang
  • Publication number: 20210287949
    Abstract: A system and method for performing in-situ measurements of semiconductor devices during chemical vapor deposition (CVD) includes disposing a chip carrier within a sealed chamber of a reactor for carrying out in-situ monitoring of partially fabricated semiconductor devices. The chip carrier includes a plurality of metallized bonding pads disposed along both peripheral edges on a same surface of the base for making electrical connections to metallized pads or contacts on the semiconductor device through bonding wires. Each of the plurality of metallized bonding pads disposed along both peripheral edges is electrically connected to each other as a pair through electrically connecting to a corresponding pair of ports which are disposed along both peripheral edges of the chip carrier. In-situ monitoring of the partially fabricated semiconductor device is performed through connecting the plurality of ports on the chip carrier to an external source-measure unit through a connector and wire harness.
    Type: Application
    Filed: March 10, 2021
    Publication date: September 16, 2021
    Inventors: Michael J. Moody, Lincoln J. Lauhon, Ju Ying Shang
  • Patent number: 9515257
    Abstract: In one aspect of the invention, the memristor includes a monolayer film formed of an atomically thin material, where the monolayer film has at least one grain boundary (GB), a first electrode and a second electrode electrically coupled with the monolayer film to define a memristor channel therebetween, such that the at least one GB is located in the memristor channel, and a gate electrode capacitively coupled with the memristor channel.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: December 6, 2016
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Mark C. Hersam, Vinod K. Sangwan, Deep M. Jariwala, In Soo Kim, Tobin J. Marks, Lincoln J. Lauhon
  • Publication number: 20160248007
    Abstract: In one aspect of the invention, the memristor includes a monolayer film formed of an atomically thin material, where the monolayer film has at least one grain boundary (GB), a first electrode and a second electrode electrically coupled with the monolayer film to define a memristor channel therebetween, such that the at least one GB is located in the memristor channel, and a gate electrode capacitively coupled with the memristor channel.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 25, 2016
    Inventors: Mark C. Hersam, Vinod K. Sangwan, Deep M. Jariwala, In Soo Kim, Tobin J. Marks, Lincoln J. Lauhon
  • Publication number: 20100155698
    Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components.
    Type: Application
    Filed: June 26, 2009
    Publication date: June 24, 2010
    Applicant: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Xiangfeng Duan, Yi Cui, Yu Huang, Mark Gudiksen, Lincoln J. Lauhon, Jianfang Wang, Hongkun Park, Qingqiao Wei, Wenjie Liang, David C. Smith, Deli Wang, Zhaohui Zhong
  • Publication number: 20090057650
    Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components.
    Type: Application
    Filed: February 27, 2008
    Publication date: March 5, 2009
    Applicant: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Xiangfeng Duan, Yi Cui, Yu Huang, Mark Gudiksen, Lincoln J. Lauhon, Jianfang Wang, Hongkun Park, Qingqiao Wei, Wenjie Liang, David C. Smith, Deli Wang, Zhaohui Zhong
  • Patent number: 7301199
    Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: November 27, 2007
    Assignee: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Xiangfeng Duan, Yi Cui, Yu Huang, Mark Gudiksen, Lincoln J. Lauhon, Jianfang Wang, Hongkun Park, Qingqiao Wei, Wenjie Liang, David C. Smith, Deli Wang, Zhaohui Zhong
  • Publication number: 20030089899
    Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components.
    Type: Application
    Filed: July 16, 2002
    Publication date: May 15, 2003
    Inventors: Charles M. Lieber, Xiangfeng Duan, Yi Cui, Yu Huang, Mark Gudiksen, Lincoln J. Lauhon, Jianfang Wang, Hongkun Park, Qingqiao Wei, Wenjie Liang, David C. Smith, Deli Wang, Zhaohui Zhong