Patents by Inventor Lincoln O'Riain
Lincoln O'Riain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9257448Abstract: An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.Type: GrantFiled: June 9, 2014Date of Patent: February 9, 2016Assignee: Infineon Technologies AGInventors: Matthias Stecher, Hans Weber, Lincoln O'Riain, Birgit von Ehrenwall
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Patent number: 9000520Abstract: A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface.Type: GrantFiled: February 11, 2014Date of Patent: April 7, 2015Assignee: Infineon Technologies Dresden GmbHInventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain
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Publication number: 20140287560Abstract: An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.Type: ApplicationFiled: June 9, 2014Publication date: September 25, 2014Inventors: Matthias Stecher, Hans Weber, Lincoln O'Riain, Birgit von Ehrenwall
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Publication number: 20140159154Abstract: A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface.Type: ApplicationFiled: February 11, 2014Publication date: June 12, 2014Inventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain
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Patent number: 8749018Abstract: An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.Type: GrantFiled: June 21, 2010Date of Patent: June 10, 2014Assignee: Infineon Technologies AGInventors: Matthias Stecher, Hans Weber, Lincoln O'Riain, Birgit von Ehrenwall
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Patent number: 8686505Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.Type: GrantFiled: July 27, 2012Date of Patent: April 1, 2014Assignee: Infineon Technologies Dresden GmbHInventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain
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Publication number: 20140027848Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: INFINEON TECHNOLOGIES DRESDEN GMBHInventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain
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Patent number: 8115279Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.Type: GrantFiled: April 28, 2010Date of Patent: February 14, 2012Assignee: Infineon Technologies AGInventors: Armin Tilke, Cajetan Wagner, Lincoln O'Riain
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Publication number: 20110309441Abstract: An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Matthias Stecher, Hans Weber, Lincoln O'Riain, Birgit von Ehrenwall
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Publication number: 20100207238Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.Type: ApplicationFiled: April 28, 2010Publication date: August 19, 2010Inventors: Armin Tilke, Cajetan Wagner, Lincoln O'Riain
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Patent number: 7749859Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.Type: GrantFiled: June 29, 2007Date of Patent: July 6, 2010Assignee: Infineon Technologies AGInventors: Armin Tilke, Cajetan Wagner, Lincoln O'Riain
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Publication number: 20090001502Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Inventors: Armin Tilke, Cajetan Wagner, Lincoln O'Riain
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Patent number: 6908831Abstract: A method for encapsulating a filling in a trench of a semiconductor substrate includes providing a first barrier layer in a trench and a second barrier layer disposed above the first barrier layer. The trench is filled with a filling, which is subsequently etched back in an upper trench section, so that a hole is produced and a filling residue remains in a lower trench section. Subsequently, a non-conformal cover layer is provided in an upper trench section, so that the cover layer of a bottom region has a first thickness greater than a second thickness of a wall region of the cover layer. The cover layer and the second barrier layer are isotropically etched-back and removed from the upper trench section, and the first barrier layer remains. The bottom region remains covered resulting in the filling residue being encapsulated by the first barrier layer and the residual cover layer.Type: GrantFiled: October 15, 2004Date of Patent: June 21, 2005Assignee: Infineon Technologies AGInventors: Lincoln O'Riain, Jörg Radecker
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Publication number: 20050095788Abstract: A method for encapsulating a filling in a trench of a semiconductor substrate includes providing a first barrier layer in a trench and a second barrier layer disposed above the first barrier layer. The trench is filled with a filling, which is subsequently etched back in an upper trench section, so that a hole is produced and a filling residue remains in a lower trench section. Subsequently, a non-conformal cover layer is provided in an upper trench section, so that the cover layer of a bottom region has a first thickness greater than a second thickness of a wall region of the cover layer. The cover layer and the second barrier layer are isotropically etched-back and removed from the upper trench section, and the first barrier layer remains. The bottom region remains covered resulting in the filling residue being encapsulated by the first barrier layer and the residual cover layer.Type: ApplicationFiled: October 15, 2004Publication date: May 5, 2005Inventors: Lincoln O'Riain, Jorg Radecker