Abstract: Technologies are presented that optimize graphics power-performance efficiency. A method of graphics processing may include beginning a graphics workload with a first voltage and a first clamping threshold; monitoring amounts of time that bursts of dynamic capacitance remain above the first clamping threshold; and, if the dynamic capacitance remains above the first clamping threshold for more than a predetermined time threshold, setting the voltage to a second voltage and setting the clamping threshold to a second clamping threshold until the end of the frame. If, at the end of an initial frame, a number of clock cycles from a start of the frame to when the predetermined time threshold is exceeded is less than a predetermined minimum number of clock cycles, the second clamping threshold and the second voltage may be maintained for processing of a predetermined number of subsequent frames.

Abstract: Technologies are presented that optimize graphics processing performance. A method of frequency scaling may include beginning a graphics workload with a starting geometry preprocessing frequency of a multiple of a streaming shader engine frequency where the multiple is non-zero; determining a primitive start pitch for a primitive of the graphics workload; comparing the determined primitive start pitch to a predetermined threshold and, if it exceeds the predetermined threshold: reducing the geometry preprocessing frequency, and, at the start of the next primitive, setting the geometry preprocessing frequency back to the starting geometry preprocessing frequency; and repeating the determining and comparing for each remaining primitive until an end of the graphics workload. Performance gain based on primitive start pitch information may also be determined.

Abstract: Methods and apparatus relating to a current change mitigation policy for limiting voltage droop in graphics logic are described. In an embodiment, logic inserts one or more bubbles in one or more Execution Unit (EU) logic pipelines or one or more sampler logic pipelines of a processor. The bubbles at least temporarily reduce execution of operations in one or more subsystems of the processor based at least partially on a comparison of a first value and one or more clamping threshold values. The first value is determined based at least partially on a summation of products of one or more event counts and dynamic capacitance weights for one or more subsystems of the processor. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to programmable power performance optimization for graphics cores are described. In one embodiment, the first frame of a scene is analyzed. It is then determined whether to optimize one or more operations, to be performed on one or more frames of the scene, based on the second frame of the scene and an idle status of one or more subsystems of a processor. And, one or more optimization operations are performed on a third frame of the scene based on the determination of whether to optimize the one or more operations. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to clamping or reducing of dynamic capacitance for graphics logic are described. In one embodiment, utilization values for a plurality of subsystems of a graphics logic are determined and a first capacitance value is in turn determined based on (e.g., a sum of products of) the determined utilization values (e.g., and one or more capacitance weight values). A second capacitance value (e.g., corresponding to a maximum dynamic capacitance or Cdyn_max corresponding to the graphics logic) is modified based on (e.g., a comparison of the first capacitance value and a (e.g., threshold) capacitance value. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to programmable power performance optimization for graphics cores are described. In one embodiment, the first frame of a scene is analyzed. It is then determined whether to optimize one or more operations, to be performed on one or more frames of the scene, based on the second frame of the scene and an idle status of one or more subsystems of a processor. And, one or more optimization operations are performed on a third frame of the scene based on the determination of whether to optimize the one or more operations. Other embodiments are also disclosed and claimed.

Abstract: Technologies are presented that optimize graphics processing performance. A method of frequency scaling may include beginning a graphics workload with a starting geometry preprocessing frequency of a multiple of a streaming shader engine frequency where the multiple is non-zero; determining a primitive start pitch for a primitive of the graphics workload; comparing the determined primitive start pitch to a predetermined threshold and, if it exceeds the predetermined threshold: reducing the geometry preprocessing frequency, and, at the start of the next primitive, setting the geometry preprocessing frequency back to the starting geometry preprocessing frequency; and repeating the determining and comparing for each remaining primitive until an end of the graphics workload. Performance gain based on primitive start pitch information may also be determined.

Abstract: Technologies are presented that optimize graphics power-performance efficiency. A method of graphics processing may include beginning a graphics workload with a first voltage and a first clamping threshold; monitoring amounts of time that bursts of dynamic capacitance remain above the first clamping threshold; and, if the dynamic capacitance remains above the first clamping threshold for more than a predetermined time threshold, setting the voltage to a second voltage and setting the clamping threshold to a second clamping threshold until the end of the frame. If, at the end of an initial frame, a number of clock cycles from a start of the frame to when the predetermined time threshold is exceeded is less than a predetermined minimum number of clock cycles, the second clamping threshold and the second voltage may be maintained for processing of a predetermined number of subsequent frames.

Abstract: Methods and apparatus relating to a current change mitigation policy for limiting voltage droop in graphics logic are described. In an embodiment, logic inserts one or more bubbles in one or more Execution Unit (EU) logic pipelines or one or more sampler logic pipelines of a processor. The bubbles at least temporarily reduce execution of operations in one or more subsystems of the processor based at least partially on a comparison of a first value and one or more clamping threshold values. The first value is determined based at least partially on a summation of products of one or more event counts and dynamic capacitance weights for one or more subsystems of the processor. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to clamping or reducing of dynamic capacitance for graphics logic are described. In one embodiment, utilization values for a plurality of subsystems of a graphics logic are determined and a first capacitance value is in turn determined based on (e.g., a sum of products of) the determined utilization values (e.g., and one or more capacitance weight values). A second capacitance value (e.g., corresponding to a maximum dynamic capacitance or Cdyn_max corresponding to the graphics logic) is modified based on (e.g., a comparison of the first capacitance value and a (e.g., threshold) capacitance value. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to rotational graphics sub-slice and Execution Unit (EU) power down to improve power performance efficiency are described. In one embodiment, power-gating is rotated amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic. The computational logic includes the plurality of slices and each of the plurality of slices includes a plurality of sub-slices to perform one or more computations. Other embodiments are also disclosed and claimed.

Abstract: A method of providing a programmer with a visualization of power usage. The method is especially suitable for integration within a debugging process (FIG. 20). A windows-type display (160, 170, 180, 190) displays sections of computer code (160a, 170a), as well as numerical values representing power usage (160b, 170b). Next to each section of code, some sort of visual representation of power usage is displayed, such as a bar of a bar graph (160c, 170c). Alternatively, the code can be highlighted if power usage exceeds a given threshold, or comments can be provided next to the code for optimizing power usage.

Abstract: A method of optimizing assembly code of a VLIW processor (10) or other processor that uses multiple-instruction words (20), each of which comprise instructions to be executed on different functional units (11d and 11e) of the processor (10). The instruction words (20) are modified, by modifying NOP instructions to minimize bit changes from cycle to cycle in the machine code. Specifically, a NOP is replaced with a proxy NOP, whose syntax is the same as an adjacent instruction but that is treated as a NOP. This modification results in reduced power dissipation.

Abstract: A method of optimizing assembly code of a VLIW processor (10) or other processor that uses multiple-instruction words (20), each of which comprise instructions to be executed on different functional units (11d and 11e) of the processor (10). The instruction words (20) are modified, such that NOPs instructions are aligned in the same slot from one instruction to the next for a series of instructions. This modification permits memory access to be disabled so that those instructions are not fetched.

Abstract: A method of optimizing assembly code of a VLIW processor (10) or other processor that uses multiple-instruction words (20), each of which comprise instructions to be executed on different functional units (11d and 11e) of the processor (10). The instruction words (20) are modified in accordance with one or more code optimization techniques (FIG. 6). Typically, the modifications tend to result in fewer cycle-to-cycle bit changes in the machine code, which results in reduced power consumption.

Abstract: A method for determining the power consumption, resulting from execution of a block of code, of an integrated circuit that includes a processor module and one or more other circuit modules. The method involves the steps of, first, providing a set of average current values for each of said modules, for a predetermined plurality of sets of conditions based on predetermined sets of signal line states associated with said module, for each instruction in the instruction set of said processor module, said sets of conditions being selected for dominant power consumption effect on the module. For each module, for each instruction in a block of code to be executed on said processor module, a set of signal line states is generated, associated with said module, for each processor cycle, in sequence. The generated set of signal line states are then tested for said set of conditions. One of said average current values is assigned for each condition so tested that is met.