Patents by Inventor Linda Pei Ei Chua

Linda Pei Ei Chua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8349657
    Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar.
    Type: Grant
    Filed: March 18, 2012
    Date of Patent: January 8, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Reza A. Pagaila, Linda Pei Ei Chua
  • Publication number: 20120175770
    Abstract: A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar.
    Type: Application
    Filed: March 18, 2012
    Publication date: July 12, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Byung Tai Do, Reza A. Pagaila, Linda Pei Ei Chua