Patents by Inventor Linda Susan Brush

Linda Susan Brush has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6215168
    Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conductivity type disposed on the substrate. The upper layer includes an active region that comprises a well region of a second, opposite conductivity type and an edge passivation zone comprising a junction termination extension (JTE) JTE region that includes portions extending away from and extending beneath the well region. The JTE region is of varying dopant density, the dopant density being maximum at a point substantially directly beneath the junction at the upper surface of the upper layer of the JTE region with the well region. The dopant density of the JTE region decreases in both lateral directions from its maximum point, becoming less in both the portions extending away from and beneath the well region.
    Type: Grant
    Filed: July 21, 1999
    Date of Patent: April 10, 2001
    Assignee: Intersil Corporation
    Inventors: Linda Susan Brush, John Mannine Savidge Neilson
  • Patent number: 6080614
    Abstract: A method of fabricating a MOS-gated semiconductor device in which arsenic dopant is implanted through a mask to form a first layer, boron dopant is implanted through the mask to form a second layer deeper than the first layer, and in which a single diffusion step diffuses the implanted arsenic and the implanted boron at the same time to form a P+ body region with an N+ source region therein and a P type channel region.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: June 27, 2000
    Inventors: John Manning Sauidge Neilson, Linda Susan Brush, Frank Stensney, John Lawrence Benjamin, Anup Bhalla, Christopher Lawrence Rexer, Richard Douglas Stokes, Christopher Boguslow Kocon, Louise E. Skurkey, Christopher Michael Scarba
  • Patent number: 5877044
    Abstract: A gate electrode control structure of an MOS-gated semiconductor device includes four doped regions including a first (source) region forming a first P-N junction with an enclosing composite region comprising a second, lightly doped (channel) region wholly enclosing a third heavily doped (body) region partly enclosing the first region, and a fourth (drain) region forming a P-N junction with the third region. The gate electrode control structure is fabricated using known gate electrode self-alignment doping processes but wherein, in the process for forming the third heavily doped region, a spacer layer is provided on the gate electrode for defining a spacing between the third region and the channel region with an improved degree of precision.
    Type: Grant
    Filed: March 11, 1997
    Date of Patent: March 2, 1999
    Assignee: Harris Corporation
    Inventors: John Manning Savidge Neilson, Christopher Boguslaw Kocon, Richard Douglas Stokes, Linda Susan Brush, John Lawrence Benjamin, Louise Ellen Skurkey, Christopher Lawrence Rexer