Patents by Inventor Linda Van Leuken-Peters
Linda Van Leuken-Peters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9590027Abstract: The present invention relates to a method for fabricating an electronic component, comprising fabricating, on a substrate (102) at least one integrated MIM capacitor (114) having a top capacitor electrode (118) and a bottom capacitor electrode (112) at a smaller distance from the substrate than the top capacitor electrode; fabricating an electrically insulating first cover layer (120) on the top capacitor electrode, which first cover layer partly or fully covers the top capacitor electrode and is made of a lead-containing dielectric material; thinning the first cover layer; fabricating an electrically insulating second cover layer (124) on the first cover layer, which second cover layer partly or fully covers the first cover layer and has a dielectric permittivity smaller than that of the first cover layer; and fabricating an electrically conductive resistor layer (126) on the second cover layer, which resistor layer has a defined ohmic resistance.Type: GrantFiled: April 14, 2010Date of Patent: March 7, 2017Assignee: NXP B.V.Inventors: Aarnoud Laurens Roest, Linda Van Leuken-Peters
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Patent number: 8901705Abstract: The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.Type: GrantFiled: October 22, 2009Date of Patent: December 2, 2014Assignee: NXP, B.V.Inventors: Aarnoud Laurens Roest, Mareike Klee, Rudiger Gunter Mauczok, Linda Van Leuken-Peters, Robertus Adrianus Maria Wolters
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Patent number: 8659124Abstract: The invention relates to a semiconductor device comprising a physical structure (50) for use in a physical unclonable function, wherein the physical structure (50) comprises a lead-zirconium titanate layer (25), and a silicon-comprising dielectric layer (27) deposited on the lead-zirconium-titanate layer (25), wherein the silicon-comprising dielectric layer (27) has a rough surface (SR), the physical structure (50) further comprising a conductive layer (30) provided on the rough surface (SR) of the silicon-comprising dielectric layer (27). The invention further relates to a method of manufacturing such semiconductor device. The invention also relates to a card, such as a smartcard, and to a RFID tag comprising such semiconductor device. The inventors have found that depositing of a silicon- comprising dielectric layer (27) on a lead-zirconium titanate layer (25) using vapor deposition results in a silicon-comprising dielectric layer (27) having a rough surface (SR).Type: GrantFiled: December 21, 2009Date of Patent: February 25, 2014Assignee: NXP B.V.Inventors: Aarnoud Laurens Roest, Linda Van Leuken-Peters, Robertus Andrianus Maria Wolters
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Patent number: 8570706Abstract: An electronic device includes a metal-insulator-metal capacitive device. In connection with an example embodiment, a metal-insulator-metal (MIM) capacitor device is in a substrate having a surface and a three dimensional structure with high aspect ratio sidewalls. The MIM capacitor device includes a first capacitor electrode including a platinum group metal (PGM)-based layer and a Ta-based layer that is between the PGM-based layer and one of the sidewalls. The MIM capacitor also includes a second capacitor electrode and an insulator material between the first and second electrodes.Type: GrantFiled: August 23, 2010Date of Patent: October 29, 2013Assignee: NXP B.V.Inventors: Willem F. A. Besling, Aarnoud L. Roest, Klaus Reimann, Linda van Leuken-Peters
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Publication number: 20120044612Abstract: An electronic device includes a metal-insulator-metal capacitive device. In connection with an example embodiment, a metal-insulator-metal (MIM) capacitor device is in a substrate having a surface and a three dimensional structure with high aspect ratio sidewalls. The MIM capacitor device includes a first capacitor electrode including a platinum group metal (PGM)-based layer and a Ta-based layer that is between the PGM-based layer and one of the sidewalls. The MIM capacitor also includes a second capacitor electrode and an insulator material between the first and second electrodes.Type: ApplicationFiled: August 23, 2010Publication date: February 23, 2012Applicant: NXP B.V.Inventors: Willem F. A. Besling, Aarnoud L. Roest, Klaus Reimann, Linda van Leuken-Peters
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Publication number: 20120045881Abstract: The present invention relates to a method for fabricating an electronic component, comprising fabricating, on a substrate (102) at least one integrated MIM capacitor (114) having a top capacitor electrode (118) and a bottom capacitor electrode (112) at a smaller distance from the substrate than the top capacitor electrode; fabricating an electrically insulating first cover layer (120) on the top capacitor electrode, which first cover layer partly or fully covers the top capacitor electrode and is made of a lead-containing dielectric material; thinning the first cover layer; fabricating an electrically insulating second cover layer (124) on the first cover layer, which second cover layer partly or fully covers the first cover layer and has a dielectric permittivity smaller than that of the first cover layer; and fabricating an electrically conductive resistor layer (126) on the second cover layer, which resistor layer has a defined ohmic resistance.Type: ApplicationFiled: April 14, 2010Publication date: February 23, 2012Applicant: NXP B.V.Inventors: Aarnoud Laurens Roest, Linda Van Leuken-Peters
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Publication number: 20110254141Abstract: The invention relates to a semiconductor device comprising a physical structure (50) for use in a physical unclonable function, wherein the physical structure (50) comprises a lead-zirconium titanate layer (25), and a silicon-comprising dielectric layer (27) deposited on the lead-zirconium-titanate layer (25), wherein the silicon-comprising dielectric layer (27) has a rough surface (SR), the physical structure (50) further comprising a conductive layer (30) provided on the rough surface (SR) of the silicon-comprising dielectric layer (27). The invention further relates to a method of manufacturing such semiconductor device. The invention also relates to a card, such as a smartcard, and to a RFID tag comprising such semiconductor device. The inventors have found that depositing of a silicon- comprising dielectric layer (27) on a lead-zirconium titanate layer (25) using vapor deposition results in a silicon-comprising dielectric layer (27) having a rough surface (SR).Type: ApplicationFiled: December 21, 2009Publication date: October 20, 2011Applicant: NXP B.V.Inventors: Aarnoud Laurens Roest, Linda Van Leuken-Peters, Robertus Andrianus Maria Wolters
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Publication number: 20110204480Abstract: The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.Type: ApplicationFiled: October 22, 2009Publication date: August 25, 2011Applicant: NXP B.V.Inventors: Aarnoud Laurens Roest, Mareike Klee, Rudiger Gunter Mauczok, Linda Van Leuken-Peters, Robertus Adrianus Maria Wolters