Patents by Inventor Linda Weyhing

Linda Weyhing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for conveying service latency requirements for devices connected to low power input/output sub-systems
    Patent number: 9158357
    Abstract: In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected to a platform from a software latency register if a software latency tolerance register mode is active. The apparatus may also include means for communicating the latency tolerance value from a hardware latency register if a host controller is active. The latency tolerance value can be sent to a power management controller. More specific examples can include means for communicating a latency tolerance value from the software latency register if the software latency tolerance register mode is not active and the host controller is not active. The apparatus can also include means for mapping a resource space in the software latency register for the device using a BIOS/platform driver. The mapping can be achieved using an advanced configuration and power interface device description.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Jaya L. Jeyaseelan, Linda Weyhing, Rajeev Nalawadi, Barnes Cooper, Suraj Varma, Nevo Idan, David Poisner
  • SYSTEM AND METHOD FOR CONVEYING SERVICE LATENCY REQUIREMENTS FOR DEVICES CONNECTED TO LOW POWER INPUT/OUTPUT SUB-SYSTEMS
    Publication number: 20140189391
    Abstract: In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected to a platform from a software latency register if a software latency tolerance register mode is active. The apparatus may also include means for communicating the latency tolerance value from a hardware latency register if a host controller is active. The latency tolerance value can be sent to a power management controller. More specific examples can include means for communicating a latency tolerance value from the software latency register if the software latency tolerance register mode is not active and the host controller is not active. The apparatus can also include means for mapping a resource space in the software latency register for the device using a BIOS/platform driver. The mapping can be achieved using an advanced configuration and power interface device description.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Jaya L. Jeyaseelan, Linda Weyhing, Rajeev Nalawadi, Barnes Cooper, Suraj Varma, Nevo Idan, David Poisner