Patents by Inventor Linden Cornett
Linden Cornett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11831742Abstract: Methods, apparatus, and systems for implementing a semi-flexible Receive Segment Coalescing (RSC) control path. Logic for evaluating packet coalescing open flow criteria and close flow criteria are implemented in hardware on a network device that receives packets from one or more networks. packet coalescing open profiles and packet coalescing close profiles are also stored on the network device, wherein each packet coalescing open profile defines a set of packet coalescing open flow criteria to be applied for that packet coalescing open profile and each packet coalescing close profile defines a set of packet coalescing close flow criteria to be applied for that packet coalescing open profile. packet coalescing open flow and close flow profiles are then assigned to packet coalescing-enabled receive queues on the network device and corresponding open and flow criteria are used to perform packet coalescing-related processing of packets in the receive queues.Type: GrantFiled: December 12, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Linden Cornett, Anjali Singhai Jain, Noam Elati
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Patent number: 11805081Abstract: Packets received non-contiguously from a network are processed by a network interface controller by coalescing received packet payload into receive buffers on a receive buffer queue and writing descriptors associated with the receive buffers for a same flow consecutively in a receive completion queue. System performance is optimized by reusing a small working set of provisioned receive buffers to minimize the memory footprint of memory allocated to store packet data. The remainder of the provisioned buffers are in an overflow queue and can be assigned to the network interface controller if the small working set of receive buffers is not sufficient to keep up with the received packet rate. The receive buffer queue can be refilled based on either timers or when the number of buffers in the receive buffer queue is below a configurable low watermark.Type: GrantFiled: March 2, 2020Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Linden Cornett, Noam Elati, Anjali Singhai Jain, Parthasarathy Sarangam, Eliel Louzoun, Manasi Deval
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Patent number: 11797333Abstract: Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located.Type: GrantFiled: December 11, 2019Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Linden Cornett, Anil Vasudevan, Parthasarathy Sarangam, Kiran Patil
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Patent number: 11681625Abstract: Examples described herein can be used to allocate replacement receive buffers for use by a network interface, switch, or accelerator. Multiple refill queues can be used to receive identifications of available receive buffers. A refill processor can select one or more identifications from a refill queue and allocate the identifications to a buffer queue. None of the refill queues is locked from receiving identifications of available receive buffers but merely one of the refill buffers is accessed at a time to provide identifications of available receive buffers. Identifications of available receive buffers from the buffer queue are provide to the network interface, switch, or accelerator to store content of received packets.Type: GrantFiled: December 16, 2019Date of Patent: June 20, 2023Assignee: Intel CorporationInventors: Linden Cornett, Parthasarathy Sarangam, Jesse Brandeburg
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Patent number: 11429413Abstract: Technologies for dynamic statistics management include a computing device with a network interface controller (NIC) and a compute engine having a memory. The NIC is to provision a counter window to a software consumer executing in the computing device. The counter window is used to track a plurality of active counters associated with a network flow. The NIC determines whether one or more flush criteria are triggered. In so determining, the NIC transfers a value for each active counter to the memory, where global counter values are maintained.Type: GrantFiled: March 30, 2018Date of Patent: August 30, 2022Assignee: Intel CorporationInventors: Linden Cornett, Parthasarathy Sarangam
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Publication number: 20220029929Abstract: Examples described herein relate to one or more processors, when operational, to execute instructions stored in memory device, to cause performance of: execute a driver that is to: negotiate capabilities of hardware with a control plane for a virtualized execution environment and limit capabilities of the hardware available to the virtualized execution environment based on a service level agreement (SLA) associated with the virtualized execution environment. In some examples, the driver is to advertise hardware capabilities requested by the virtualized execution environment. In some examples, the control plane is to set capabilities of a hardware available to the virtualized execution environment based on the SLA.Type: ApplicationFiled: October 1, 2021Publication date: January 27, 2022Inventors: Anjali Singhai JAIN, Daniel DALY, Sridhar SAMUDRALA, Linden CORNETT, Phani BURRA, Brett CREELEY
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Patent number: 10768841Abstract: Technologies for managing network statistic counters include a network interface controller (NIC) of a computing device configured to identify a statistic counter of and a software consumer associated with a received network packet and identify an active counter page as a function of the identified software consumer. The NIC is further configured to read a value of the statistic counter stored at a counter memory address of a corresponding counter identifier entry of the identified active counter page, increment a read value of the statistic counter, and write the incremented value of the statistic counter back to the counter memory address. Additionally, in response to detecting a notification triggering event, generating a notification message that includes a present value of the statistic counter and a present value of each of the other statistic counters of the active counter page, and transmit the generated notification message to the software consumer. Other embodiments are described herein.Type: GrantFiled: September 30, 2017Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: Linden Cornett, Chih-Jen Chang, Manasi Deval, Parthasarathy Sarangam, Naru D. Sundar, Padma Akkiraju, Alexander Nguyen
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Publication number: 20200210359Abstract: Examples described herein relate to a device indicating a number of available interrupt messages that is more than physical resources available to store the available interrupt messages and allocating one or more physical resources to provide one or more interrupt messages based on allocation of the one or more interrupt messages to a destination entity. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level and allocate the requested maximum permitted allocation of interrupt messages for use in a configuration region of a device. However, based on unavailability of a physical resource to store a first interrupt message, allocation of the first interrupt message to a destination entity may not be permitted.Type: ApplicationFiled: March 10, 2020Publication date: July 2, 2020Inventors: Linden CORNETT, Eliel LOUZOUN, Anjali Singhai JAIN, Ronen Aharon HYATT, Danny VOLKIND, Noam ELATI, Nadav TURBOVICH
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Publication number: 20200204503Abstract: Packets received non-contiguously from a network are processed by a network interface controller by coalescing received packet payload into receive buffers on a receive buffer queue and writing descriptors associated with the receive buffers for a same flow consecutively in a receive completion queue. System performance is optimized by reusing a small working set of provisioned receive buffers to minimize the memory footprint of memory allocated to store packet data. The remainder of the provisioned buffers are in an overflow queue and can be assigned to the network interface controller if the small working set of receive buffers is not sufficient to keep up with the received packet rate. The receive buffer queue can be refilled based on either timers or when the number of buffers in the receive buffer queue is below a configurable low watermark.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Inventors: Linden CORNETT, Noam ELATI, Anjali Singhai JAIN, Parthasarathy SARANGAM, Eliel LOUZOUN, Manasi DEVAL
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Publication number: 20200183732Abstract: Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located.Type: ApplicationFiled: December 11, 2019Publication date: June 11, 2020Inventors: Linden Cornett, Anil Vasudevan, Parthasarathy Sarangam, Kiran Patil
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Publication number: 20200120190Abstract: Methods, apparatus, and systems for implementing a semi-flexible Receive Segment Coalescing (RSC) control path. Logic for evaluating packet coalescing open flow criteria and close flow criteria are implemented in hardware on a network device that receives packets from one or more networks. packet coalescing open profiles and packet coalescing close profiles are also stored on the network device, wherein each packet coalescing open profile defines a set of packet coalescing open flow criteria to be applied for that packet coalescing open profile and each packet coalescing close profile defines a set of packet coalescing close flow criteria to be applied for that packet coalescing open profile. packet coalescing open flow and close flow profiles are then assigned to packet coalescing-enabled receive queues on the network device and corresponding open and flow criteria are used to perform packet coalescing-related processing of packets in the receive queues.Type: ApplicationFiled: December 12, 2019Publication date: April 16, 2020Inventors: Linden Cornett, Anjali Singhai Jain, Noam Elati
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Publication number: 20200117605Abstract: Examples described herein can be used to allocate replacement receive buffers for use by a network interface, switch, or accelerator. Multiple refill queues can be used to receive identifications of available receive buffers. A refill processor can select one or more identifications from a refill queue and allocate the identifications to a buffer queue. None of the refill queues is locked from receiving identifications of available receive buffers but merely one of the refill buffers is accessed at a time to provide identifications of available receive buffers. Identifications of available receive buffers from the buffer queue are provide to the network interface, switch, or accelerator to store content of received packets.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Linden CORNETT, Parthasarathy Sarangam, Jesse Brandeburg
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Patent number: 10346326Abstract: Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.Type: GrantFiled: January 27, 2016Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Yadong Li, Linden Cornett, Manasi Deval, Anil Vasudevan, Parthasarathy Sarangam
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Publication number: 20190042293Abstract: Technologies for dynamic statistics management include a computing device with a network interface controller (NIC) and a compute engine having a memory. The NIC is to provision a counter window to a software consumer executing in the computing device. The counter window is used to track a plurality of active counters associated with a network flow. The NIC determines whether one or more flush criteria are triggered. In so determining, the NIC transfers a value for each active counter to the memory, where global counter values are maintained.Type: ApplicationFiled: March 30, 2018Publication date: February 7, 2019Inventors: Linden Cornett, Parthasarathy Sarangam
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Patent number: 10015117Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.Type: GrantFiled: July 17, 2015Date of Patent: July 3, 2018Assignee: Intel CorporationInventors: Linden Cornett, David B. Minturn, Sujoy Sen, Hemal V. Shah, Anshuman Thakur, Gary Tsao, Anil Vasudevan
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Publication number: 20180159803Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.Type: ApplicationFiled: December 5, 2017Publication date: June 7, 2018Applicant: Intel CorporationInventors: Linden Cornett, David B. Minturn, Sujoy Sen, Hemal V. Shah, Anshuman Thakur, Gary Y. Tsao, Anil Vasudevan
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Publication number: 20180152366Abstract: Technologies for managing network statistic counters include a network interface controller (NIC) of a computing device configured to identify a statistic counter of and a software consumer associated with a received network packet and identify an active counter page as a function of the identified software consumer. The NIC is further configured to read a value of the statistic counter stored at a counter memory address of a corresponding counter identifier entry of the identified active counter page, increment a read value of the statistic counter, and write the incremented value of the statistic counter back to the counter memory address. Additionally, in response to detecting a notification triggering event, generating a notification message that includes a present value of the statistic counter and a present value of each of the other statistic counters of the active counter page, and transmit the generated notification message to the software consumer. Other embodiments are described herein.Type: ApplicationFiled: September 30, 2017Publication date: May 31, 2018Inventors: Linden Cornett, Chih-Jen Chang, Manasi Deval, Parthasarathy Sarangam, Naru D. Sundar, Padma Akkiraju, Alexander Nguyen
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Patent number: 9621633Abstract: Generally, this disclosure relates to low latency networking. A system may include processor circuitry comprising at least one processor; memory circuitry configured to store an application, a receive queue and a networking stack comprising a network device driver; a network controller comprising a flow director, the network controller configured to couple the host device to at least one link partner and the flow director configured to store one or more selected received packets in the receive queue, the selecting based, at least in part, on a packet flow identifier; and a network device driver configured to identify the receive queue in response to a polling request comprising the packet flow identifier; poll the receive queue; and process each received packet stored in the receive queue.Type: GrantFiled: March 15, 2013Date of Patent: April 11, 2017Assignee: Intel CorporationInventors: Yadong Li, Anil Vasudevan, Linden Cornett
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Patent number: 9602443Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.Type: GrantFiled: December 1, 2014Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Linden Cornett, David B. Minturn, Sujoy Sen, Hemal V. Shah, Anshuman Thakur, Gary Tsao, Anil Vasudevan
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Publication number: 20160321203Abstract: Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.Type: ApplicationFiled: January 27, 2016Publication date: November 3, 2016Applicant: Intel CorporationInventors: Yadong Li, Linden Cornett, Manasi Deval, Anil Vasudevan, Parthasarathy Sarangam