Abstract: Systems and techniques for circuit placement are described. An electronic design automation (EDA) tool can receive a netlist for the circuit design. Next, the EDA tool can represent the netlist as a graph, and perform fuzzy clustering on the graph to obtain a set of clusters and a set of probability values. The EDA tool can then partitioning and place the circuit design based on the set of clusters and the set of probability values. The EDA tool can then optimize the circuit design placement. During optimization the EDA tool can reassign at least one cell to a different layout bin based on the set of probability values.

Abstract: Systems and techniques for circuit placement are described. An electronic design automation (EDA) tool can receive a netlist for the circuit design. Next, the EDA tool can represent the netlist as a graph, and perform fuzzy clustering on the graph to obtain a set of clusters and a set of probability values. The EDA tool can then partition and place the circuit design based on the set of clusters and the set of probability values. The EDA tool can then optimize the placed circuit design. During optimization the EDA tool can reassign at least one cell to a different layout bin based on the set of probability values.

Abstract: An automated layout method allows designing advanced integrated circuits with design rules of high complexity. In particular, a hierarchical constrained layout process is applicable and useful for analog and mixed-signal integrated circuit designs and may be based on an incremental concurrent placement and routing. Use of constraints from multiple levels of a circuit description hierarchy allows computationally efficient processing of logical circuit increments and produces high-quality outcomes. Users such as circuit designers can exercise a high degree of predictability and control over the resulting physical layout construction by either user-specified or computer-generated constraints.

Abstract: An automated layout method allows designing advanced integrated circuits with design rules of high complexity. In particular, a hierarchical constrained layout process is applicable and useful for analog and mixed-signal integrated circuit designs and may be based on an incremental concurrent placement and routing. Use of constraints from multiple levels of a circuit description hierarchy allows computationally efficient processing of logical circuit increments and produces high-quality outcomes. Users such as circuit designers can exercise a high degree of predictability and control over the resulting physical layout construction by either user-specified or computer-generated constraints.

Abstract: A circuit and method for generating a local clock signal and a telecommunications system incorporating the circuit or the method. In one embodiment, the circuit includes: (1) a phase detector for receiving an input data signal, (2) (at least) first and second continuously controllable delay lines, coupled to the phase detector, for producing respective first and second candidate local clock signals and (3) delay line selector, coupled to the first and second delay lines, for selecting one of the first and second candidate local clock signals to be the local clock signal based on phase excursions in the input data signal.

Abstract: A circuit and method for generating a local clock signal and a telecommunications system incorporating the circuit or the method. In one embodiment, the circuit includes: (1) a phase detector for receiving an input data signal, (2) (at least) first and second continuously controllable delay lines, coupled to the phase detector, for producing respective first and second candidate local clock signals and (3) delay line selector, coupled to the first and second delay lines, for selecting one of the first and second candidate local clock signals to be the local clock signal based on phase excursions in the input data signal.

Abstract: A local clock signal synthesizer, a method of generating fractional frequency local clock signals and a synchronous telecommunications system incorporating the synthesizer or the method. In one embodiment, the synthesizer includes: (1) a reference clock source that generates a reference clock signal, (2) a delay circuit, coupled to the reference clock source and having taps, that provides progressively delayed versions of the reference clock signal at the taps and (3) tap-select logic, coupled to the delay circuit, that traverses the taps to generate the local clock signal from the progressively delayed versions.

Abstract: A MOSFET having a buried channel structure and an adjacent surface channel structure between a source region and a drain region. The surface channel structure is preferably formed adjacent the source region via angular implantation techniques. By combining the advantages of the surface channel device with the buried channel device, the resulting hybrid MOSFET structure has improved drive current and switching characteristics.

Abstract: The present invention comprises a method for controlling a threshold voltage through a semiconductor substrate of a first conductivity type (the type being an n- or p- type in a MOSFET) without the need for a blanket implant for either long or short channel devices. A gate structure having opposed lateral edges is formed adjacent a surface of the semiconductor substrate and over a channel region of the substrate. The substrate is rotated around a rotation axis normal to the surface of the substrate to a first rotation position. Ions of a first conductivity type are then implanted into the channel region, using the gate structure as a mask, at an oblique angle relative to the surface normal of the substrate. The substrate is then rotated to a second rotation position approximately 180 degrees from the first rotation position. Ions of the first conductivity type are then implanted into the channel region, using the gate structure as a mask, at the oblique angle relative to the surface of the substrate.