Patents by Inventor Lindsey Hall
Lindsey Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8944105Abstract: A fluid delivery apparatus includes a spout (12) located adjacent a sink basin (16). A fluid supply conduit (14) is supported by the spout (12). Capacitive sensors (29) and (41) are provided on the spout (12) and sink basin (16), respectively. A controller (26) is coupled to the capacitive sensors (29, 41) to control the amount of fluid supplied to the fluid supply conduit (14) based on outputs from the capacitive sensors (29, 41).Type: GrantFiled: January 31, 2008Date of Patent: February 3, 2015Assignee: Masco Corporation of IndianaInventors: Robert W. Rodenbeck, David M. Burke, Timothy J. Ensor, Lindsey Hall, Paul D. Koottungal
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Patent number: 8940634Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.Type: GrantFiled: June 29, 2011Date of Patent: January 27, 2015Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, Inc., STMicroelectronics, Inc.Inventors: Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Steven R. Soss, Jin Z. Wallner
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Publication number: 20150008488Abstract: A method of manufacturing a semiconductor structure includes forming a raised source-drain region in a semiconductor substrate adjacent to a dummy gate and forming a chemical mechanical polish (CMP) stop layer over the gate structure and above a top surface of the semiconductor substrate. A first ILD layer is formed above the CMP stop layer. The first ILD layer is removed to a portion of the CMP stop layer located above the gate structure and a portion of the CMP stop layer located above the gate structure is also removed to expose the dummy gate. The dummy gate is replaced with a metal gate and the metal gate is polished until the CMP stop layer located above the raised source-drain region is reached.Type: ApplicationFiled: July 2, 2013Publication date: January 8, 2015Inventors: LINDSEY HALL, VIRAJ Y. SARDESAI, CUNG D. TRAN
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Publication number: 20130241070Abstract: A semiconductor device with overlapping contacts is provided. In one aspect, the semiconductor device includes a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact.Type: ApplicationFiled: May 2, 2013Publication date: September 19, 2013Applicants: International Business Machines Corporation, STMicroelectronics, Inc., Globalfoundaries Inc.Inventors: Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Steven R. Soss, Jin Z. Wallner
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Publication number: 20130001786Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC.Inventors: Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Steven R. Soss, Jin Z. Wallner
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Patent number: 8119470Abstract: Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.Type: GrantFiled: March 21, 2007Date of Patent: February 21, 2012Assignee: Texas Instruments IncorporatedInventors: Shashank Sureshchandra Ekbote, Borna Obradovic, Lindsey Hall, Craig Huffman, Ajith Varghese
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Publication number: 20100108165Abstract: A fluid delivery apparatus includes a spout (12) located adjacent a sink basin (16). A fluid supply conduit (14) is supported by the spout (12). Capacitive sensors (29) and (41) are provided on the spout (12) and sink basin (16), respectively. A controller (26) is coupled to the capacitive sensors (29, 41) to control the amount of fluid supplied to the fluid supply conduit (14) based on outputs from the capacitive sensors (29, 41).Type: ApplicationFiled: January 31, 2008Publication date: May 6, 2010Inventors: Robert W. Rodenbeck, David M. Burke, Timothy J. Ensor, Lindsey Hall, Paul D. Koottungal
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Patent number: 7448395Abstract: The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.Type: GrantFiled: July 19, 2004Date of Patent: November 11, 2008Assignee: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Freidoon Mehrad, Lindsey Hall, Vivian Liu, Clint Montgomery, Scott Johnson
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Publication number: 20080230815Abstract: Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.Type: ApplicationFiled: March 21, 2007Publication date: September 25, 2008Inventors: Shashank Sureshchandra Ekbote, Borna Obradovic, Lindsey Hall, Craig Huffman, Ajith Varghese
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Patent number: 7422968Abstract: The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).Type: GrantFiled: July 29, 2004Date of Patent: September 9, 2008Assignee: Texas Instruments IncorporatedInventors: Jiong-Ping Lu, Clint Montgomery, Lindsey Hall, Donald Miles, Duofeng Yue, Thomas D. Bonifiield
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Publication number: 20080076191Abstract: A ferroelectric capacitor stack is formed over a metal-dielectric interconnect layer. After forming the interconnect layer, the surface of the interconnect layer is treated with gas cluster ion beam (GCIB) processing. Prior to this processing, the surface typically includes metal recesses. The GCIB processing smoothes these recesses and provides a more level surface on which to form the ferroelectric capacitor stack. When the ferroelectric capacitor stack is formed on this leveled surface, leakage is reduced and yields increased as compared to the case where GCIB processing is not used.Type: ApplicationFiled: September 22, 2006Publication date: March 27, 2008Inventors: Lindsey Hall, Sanjeev Aggarwal, Satyavolu Srinivas Papa Rao
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Patent number: 7341933Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes providing a capped polysilicon gate electrode (290) over a substrate (210), the capped polysilicon gate electrode (290) including a buffer layer (260) located between a polysilicon gate electrode layer (250) and a protective layer (270). The method further includes forming source/drain regions (710) in the substrate (210) proximate the capped polysilicon gate electrode (290), removing the protective layer (270) and the buffer layer (260), and siliciding the polysilicon gate electrode layer (250) to form a silicided gate electrode (1110).Type: GrantFiled: December 8, 2004Date of Patent: March 11, 2008Assignee: Texas Instruments IncorporatedInventors: Shaofeng Yu, Haowen Bu, Jiong-Ping Lu, Lindsey Hall
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Publication number: 20070278524Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.Type: ApplicationFiled: July 2, 2007Publication date: December 6, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Lindsey Hall
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Patent number: 7253086Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.Type: GrantFiled: October 18, 2004Date of Patent: August 7, 2007Assignee: Texas Instruments IncorporatedInventor: Lindsey Hall
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Patent number: 7244654Abstract: A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.Type: GrantFiled: July 29, 2004Date of Patent: July 17, 2007Assignee: Texas Instruments IncorporatedInventors: Pr Chidambaram, Douglas T. Grider, Brian A. Smith, Haowen Bu, Lindsey Hall
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Patent number: 7217626Abstract: Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after implanting the source/drain region (116), where the remaining sidewall spacer (120a) is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.Type: GrantFiled: July 26, 2004Date of Patent: May 15, 2007Assignee: Texas Instruments IncorporatedInventors: Haowen Bu, PR Chidambaram, Rajesh Khamankar, Lindsey Hall
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Patent number: 7157358Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, forming a polysilicon gate electrode (250) over a substrate (210) and forming a protective layer (260) over the polysilicon gate electrode (250) to provide a capped polysilicon gate electrode (230). The method further includes forming a protective oxide (510) on a surface proximate the polysilicon gate electrode (250), and removing the protective oxide (510) using a wet etch, the wet etch not having a substantial impact on the protective layer (260).Type: GrantFiled: July 2, 2004Date of Patent: January 2, 2007Assignee: Texas Instruments IncorporatedInventors: Lindsey Hall, Haowen Bu, Shaofeng Yu
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Patent number: 7153706Abstract: The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially planar ferroelectric dielectric layer (165) located over a first electrode layer (160), wherein the substantially planar ferroelectric dielectric layer (165) has an average surface roughness of less than about 4 nm. The ferroelectric capacitor (100) further includes a second electrode layer (170) located over the substantially planar ferroelectric dielectric layer (165).Type: GrantFiled: April 21, 2004Date of Patent: December 26, 2006Assignee: Texas Instruments IncorporatedInventors: Sanjeev Aggarwal, Kelly J. Taylor, Lindsey Hall, Satyavolu Srinivas Papa Rao
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Publication number: 20060258091Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).Type: ApplicationFiled: May 12, 2005Publication date: November 16, 2006Applicant: Texas Instruments Inc.Inventors: Juanita DeLoach, Lindsey Hall, Lance Robertson, Jiong-Ping Lu, Donald Miles
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Publication number: 20060134844Abstract: A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.Type: ApplicationFiled: December 20, 2004Publication date: June 22, 2006Inventors: Jiong-Ping Lu, Shaofeng Yu, Haowen Bu, Lindsey Hall, Mark Visokay