Abstract: A method includes fabricating semiconductor structures extending in a first direction and fabricating gate-conductors extending in a second direction intersecting the semiconductor structure. The method also includes patterning a first metal layer to form horizontal conducting lines extending in the first direction, and patterning the second metal layer to form vertical conducting lines extending in the second direction. A first vertical conducting line is aligned with a first gate-conductor underneath and a second vertical conducting line is aligned with a vertical boundary of a circuit cell. The first vertical conducting line is directly connected to a first horizontal conducting line through a first pin-connector, and the second vertical conducting line is directly connected to a second horizontal conducting line through a second pin-connector.

Abstract: A cathode for rare earth molten salt electrolysis is provided. The cathode includes a column. The bottom of the column includes a cone. The peak of the cone includes a sharp tip or a flat surface. When the peak of the cone is the sharp tip, an opening angle of the sharp tip is between 5 degree and 175 degree. An electrolysis system having a cathode is also provided.

Abstract: A method of fabricating a semiconductor structure provided herein includes providing a thick-metal density range for a model structure, wherein the model structure includes a wafer substrate, and layers of metal patterns stacking on the wafer substrate; modifying the thick-metal density range to constrain a warpage range of the model structure toward a target range of warpage; and fabricating the semiconductor structure by forming the layers of metal patterns on the wafer substrate, wherein a thick-metal layer among the layers of metal patterns is formed based on the modified thick-metal density range, and a thickness of the thick-metal layer is twice or more of a thickness of one of the layers of metal patterns next to the thick-metal layer. A semiconductor structure fabricating by using the above method is further provided.

Abstract: In one embodiment, a system includes a first circuit defining recesses along an edge of the first circuit board, and a second circuit board defining fins extending from at least one outer edge of the second circuit board. The fins of the second circuit board are positioned within the recesses of the second circuit board to connect the circuit boards in a co-planar manner. The fins and recesses may be shaped to provide an interlocking connection of the first and second circuit boards in the co-planar direction.

Abstract: A sensor fusion and object tracking system and a method thereof are provided. The sensor fusion and object tracking system includes a first fusion module and a second fusion module in signal communication therewith. The first fusion module performs a first fusion process on a 2D driving image and 3D point cloud information to obtain first fusion information having a plurality of recognized objects. The second fusion module performs a second fusion process on the first fusion information and radar information to obtain second fusion information containing the plurality of recognized objects. The second fusion information is used to generate a region of interest (ROI), and the recognized objects within the ROI serve as target objects in subsequent tracking.

Abstract: An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.

Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

Abstract: A lens assembly includes a first lens, a second lens, a third lens, a first reflective element, and a second reflective element. The first lens is with positive refractive power. The first reflective element includes a first surface, a second surface, and a third surface, wherein the first surface and the third lens are opposite to each other. The second reflective element includes a fourth surface, a fifth surface, and a sixth surface, wherein the fourth surface and the third surface are opposite to each other. The first lens, the second lens, the third lens, and the first reflective element are arranged in order from an object side along a first axis. The first reflective element and the second reflective element are arranged in order along a second axis. The second reflective element and an image plane are arranged in order along a third axis.

Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an interconnect structure over a substrate. The method further includes forming a passivation layer over the interconnect structure. The method further includes forming a conductive structure over the passivation layer, wherein the conductive structure includes a surrounding portion over the passivation layer, and a concave portion surrounded by the surrounding portion. A height of the surrounding portion is greater than a height of the concave portion calculated from a top surface of the passivation layer. The method further includes forming a liner over the conductive structure, wherein an oxygen-to-silicon ratio of the liner is lower than about 1.8.

Abstract: An integrated circuit (IC) device includes a circuit region, a lower metal layer over the circuit region, and an upper metal layer over the lower metal layer. The lower metal layer includes a plurality of lower conductive patterns elongated along a first axis. The upper metal layer includes a plurality of upper conductive patterns elongated along a second axis transverse to the first axis. The plurality of upper conductive patterns includes at least one input or output configured to electrically couple the circuit region to external circuitry outside the circuit region. The upper metal layer further includes a first lateral upper conductive pattern contiguous with and projecting, along the first axis, from a first upper conductive pattern among the plurality of upper conductive patterns. The first lateral upper conductive pattern is over and electrically coupled to a first lower conductive pattern among the plurality of lower conductive patterns.

Abstract: In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.

Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a substrate having a circuit region and a chip corner region; IC devices formed on the substrate within the circuit region; a passivation layer formed over the IC devices; and a polyimide layer formed over the passivation layer, wherein the passivation layer and the polyimide layer include a stress-release pattern formed in the chip corner region.

Abstract: A delta-sigma modulator is provided. The delta-sigma modulator includes a multiplexer, a modulation circuit and a demultiplexer. The multiplexer is configured to receive a first analog signal and a second analog signal, and output an input signal. The first analog signal and the second analog signal are in different electrical forms, and the multiplexer is configured to select, in a time-division manner, the first analog signal or the second analog signal as the input signal SIN to be output. The modulation circuit is configured to modulate the input signal into a digital signal. The demultiplexer has a first output terminal and a second output terminal, and selects the first output terminal or the second output terminal in a time-division manner to output the digital signal.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A lens assembly includes a lens unit and a first reflective element. The lens unit includes a plurality of lenses and the back focal length of the lens unit is longer than the total length of the lens unit. The first reflective element includes a first surface, a first prism surface, and a bottom surface, and the first prism surface connects the first surface and the bottom surface, respectively. The lens unit and the first reflective element are arranged in order from an object side along a first axis. A light from the object side enters the first reflective element from the first surface and then guided to the first prism surface.

Abstract: In an embodiment, a method includes forming a device layer over a first substrate; forming a first interconnect structure over a front-side of the device layer; attaching a second substrate to the first interconnect structure; forming a second interconnect structure over a back-side of the device layer, the second interconnect structure comprising back-side memory elements, wherein the back-side memory elements and a first plurality of active devices of the device layer provide a first memory array; and forming conductive connectors over the second interconnect structure.

Abstract: An object detection method includes steps that are to be performed for each piece of point cloud data received from a lidar module, of selecting a first to-be-combined image from among images received from a camera device that corresponds in time to the piece of point cloud data, selecting a second to-be-combined image from among the images that is the Nth image before the first to-be-combined image in the time order, combining the first to-be-combined image and the second to-be-combined image to generate a combined image, generating a result image by incorporating the piece of point cloud data into the combined image, and inputting the result image into a trained machine learning model in order to determine a class to which each object in the result image belongs.

Abstract: A furandicarboxylate polymer has a character index that ranges from 0.27 to 0.55 and that is calculated using the following Equation: Character index=[(AC1×Mn1÷(2×106)], where AC1 represents an acid value of the furandicarboxylate polymer, and Mn1 represents a number average molecular weight of the furandicarboxylate polymer.

Abstract: A semiconductor device and a semiconductor package structure are provided. The semiconductor device includes a Radio Frequency (RF) circuit, at least one Ultra Thick Metal (UTM) layer and at least one aluminum (AP) mesh layer. The UTM layer is stacked on the RF circuit. The aluminum mesh layer is stacked on the UTM layer, and the UTM layer is connected to a power source or a ground through the aluminum mesh layer.