Abstract: An optical system is provided. The optical system includes a movable part, a fixed part, and a first driving assembly, and a second driving assembly. The movable part connects an optical element. The movable part is movable relative to the fixed part. The first driving assembly and the second driving assembly is for driving the movable part to move. The first driving assembly generates a first driving force to drive the movable part to move in a first dimension. The second driving assembly generates a second driving force to drive the movable part to move in a second dimension.

Abstract: A driving mechanism includes a fixed part, a movable part, and a driving assembly. The movable part is movably connected to the fixed part for holding an optical element that has an optical axis. The driving assembly is configured to drive the movable part to move relative to the fixed part.

Abstract: A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.

Abstract: A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.

Abstract: An analog-to-digital converter (ADC) for converting an optical signal into an electrical signal is disclosed. The ADC includes a detection module, a first P-type metal oxide semiconductor (PMOS) transistor, a first N-type metal oxide semiconductor (NMOS) transistor, a first switch unit, and an output module. The first PMOS transistor and the first NMOS transistor form an inverter. The first switch unit is disposed between the input terminal and the output terminal of the inverter and is turned on/off according to a first control signal. The output module is coupled to the output terminal of the inverter for counting the time that an input voltage is greater than a reference voltage and generating a digital signal.

Abstract: An analog-to-digital converter (ADC) for converting an optical signal into an electrical signal is disclosed. The ADC includes a detection module, a first P-type metal oxide semiconductor (PMOS) transistor, a first N-type metal oxide semiconductor (NMOS) transistor, a first switch unit, and an output module. The first PMOS transistor and the first NMOS transistor form an inverter. The first switch unit is disposed between the input terminal and the output terminal of the inverter and is turned on/off according to a first control signal. The output module is coupled to the output terminal of the inverter for counting the time that an input voltage is greater than a reference voltage and generating a digital signal.

Abstract: A non-volatile memory unit includes memory units for providing a data current corresponding to stored data; a first load unit having a first end; a second load unit having a second end; and a sensing unit. The first load unit and the second load unit can receive current input to build voltages respectively at the first end and the second end. When the memory unit provides the data current, the second load unit is enabled such that the data current inputs into the first load unit and the second load unit; then the second load is disabled after a predetermined time such that the data current inputs into the first load unit only, and the sensing unit generates a data signal for data-acquisition according to a voltage difference between the voltage at the first end and a reference voltage.