Patents by Inventor Ling-Chun TSENG

Ling-Chun TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230337417
    Abstract: A method for forming a semiconductor memory structure includes the following steps. A first patterned hard mask layer is formed over a conductive material. The first patterned hard mask layer includes first strip patterns and a mesa pattern. The mesa pattern is connected with the first strip patterns. A second patterned hard mask layer is formed over the first patterned hard mask layer. The second patterned hard mask layer includes second strip patterns overlapping the first strip patterns and first wire patterns overlapping the mesa pattern. The first patterned hard mask layer is etched using the second patterned hard mask layer. The remaining portions of the first strip patterns form pad patterns. The remaining portions of the mesa pattern form second wire patterns. The pad patterns and the second wire patterns are transferred into the conductive material.
    Type: Application
    Filed: April 14, 2022
    Publication date: October 19, 2023
    Inventors: Ling-Chun TSENG, Tzu-Ming OU YANG, Pin-Han CHIU
  • Publication number: 20220415781
    Abstract: A method for forming a semiconductor memory structure includes forming a plurality of conductive wire structures over a semiconductor substrate, and forming a plurality of spacer structures along the sidewalls of the conductive wire structures. Each of the spacer structures includes a first spacer. The method also includes forming a plurality of dielectric strips across the conductive wire structures, forming a plurality of conductive strips over the conductive wire structures and the dielectric strips, performing a patterning process on the conductive strips to form a plurality of conductive pads, and removing the first spacer of each of the spacer structures to form a gap in each of the spacer structures.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Hung-Jung YAN, Ling-Chun TSENG, Chun-Chieh WANG, Tzu-Ming OU YANG
  • Patent number: 11527475
    Abstract: A memory device includes a substrate, a bit line, a first insulating film, a second insulating film, a third insulating film, and a contact. The bit line is disposed over the substrate. The first insulating film is disposed on a sidewall of the bit line. The second insulating film is disposed on the first insulating film and is made of a different material than the first insulating film. The third insulating film is disposed on the second insulating film and is made of a different material than the second insulating film. The top surfaces of the second insulating film and the third insulating film are lower than the top surface of the first insulating film. The contact is disposed over the substrate and adjacent to the bit line. The width of the lower portion of the contact is less than the width of the upper portion of the contact.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: December 13, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Ling-Chun Tseng, Shu-Ming Lee, Tzu-Ming Ou Yang
  • Publication number: 20210225763
    Abstract: A memory device includes a substrate, a bit line, a first insulating film, a second insulating film, a third insulating film, and a contact. The bit line is disposed over the substrate. The first insulating film is disposed on a sidewall of the bit line. The second insulating film is disposed on the first insulating film and is made of a different material than the first insulating film. The third insulating film is disposed on the second insulating film and is made of a different material than the second insulating film. The top surfaces of the second insulating film and the third insulating film are lower than the top surface of the first insulating film. The contact is disposed over the substrate and adjacent to the bit line. The width of the lower portion of the contact is less than the width of the upper portion of the contact.
    Type: Application
    Filed: September 30, 2020
    Publication date: July 22, 2021
    Inventors: Ling-Chun TSENG, Shu-Ming LEE, Tzu-Ming OU YANG
  • Publication number: 20190334084
    Abstract: A resistive random access memory (RRAM) structure and its manufacturing method are provided. The RRAM structure includes a bottom electrode layer formed on a substrate, a resistance switching layer formed on the bottom electrode layer, and a top electrode layer formed on the resistance switching layer. The top electrode layer forms a recess. The RRAM structure also includes a liner formed on a sidewall of the bottom electrode layer, a sidewall of the resistance switching layer, and a sidewall of the top electrode layer. The liner includes a hydrogen gas barrier material. The RRAM structure also includes an insulating layer formed on the liner. A material of the insulating layer is different from the hydrogen gas barrier material.
    Type: Application
    Filed: April 30, 2019
    Publication date: October 31, 2019
    Inventors: Tzu-Ming OU YANG, Ling-Chun TSENG, Yen-De LEE