Abstract: An airflow heating module for an equipment front-end module, including: a first perforated plate including a first plurality of holes used as airflow inlets; a second perforated plate including a second plurality of holes used as airflow outlets; a plurality of heaters provided between the first and the second perforated plates; and an active air intake device provided on the first perforated plate to accelerate airflow flowing through the first plurality of holes and past the plurality of heaters, such that the airflow carries heat generated by the heaters and passes through the second plurality of holes. Each of the heaters includes a heating tube and a fin. The fin is formed helically around the heating tube and attached thereto.

Abstract: A device includes a memory configured to store video data. The device also includes a video decoder coupled to the memory and to a cache. The video decoder is configured to decode an input frame of the video data to generate a first video frame and includes an inline downscaler configured to generate a second video frame corresponding to the first video frame downscaled for display output.

Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

Abstract: In some aspects, the present disclosure provides a method for sharing a single optical sensor between multiple image processors. In some embodiments, the method includes receiving, at a control arbiter, a first desired configuration of a first one or more desired configurations for capturing an image frame by the optical sensor, the first one or more desired configurations communicated from a primary image processor. The method may also include receiving, at the control arbiter, a second desired configuration of a second one or more desired configurations for capturing the image frame by the optical sensor, the second one or more desired configurations communicated from a secondary image processor. The method may also include determining, by the control arbiter, an actual configuration for capturing the image frame by the optical sensor, the actual configuration based on the first desired configuration and the second desired configuration.

Abstract: In some aspects, the present disclosure provides a method for sharing a single optical sensor between multiple image processors. In some embodiments, the method includes receiving, at a control arbiter, a first desired configuration of a first one or more desired configurations for capturing an image frame by the optical sensor, the first one or more desired configurations communicated from a primary image processor. The method may also include receiving, at the control arbiter, a second desired configuration of a second one or more desired configurations for capturing the image frame by the optical sensor, the second one or more desired configurations communicated from a secondary image processor. The method may also include determining, by the control arbiter, an actual configuration for capturing the image frame by the optical sensor, the actual configuration based on the first desired configuration and the second desired configuration.

Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

Abstract: The present disclosure relates to methods and apparatus for graphics processing. In some aspects, multiple processing units can be in a graphics processing pipeline of a GPU. The apparatus can also group the multiple processing units into one or more processing unit clusters. In some aspects, each of the one or more processing unit clusters can correspond to one or more context registers. Additionally, the apparatus can determine one or more context states of the one or more context registers in each of the one or more processing unit clusters. Also, the apparatus can implement one or more execution counters corresponding to at least one of the one or more processing unit clusters in the graphics processing pipeline, where each of the one or more execution counters includes an execution value.

Abstract: Systems and methods for interleaving video sub-blocks in video coding are described herein. In one aspect, an apparatus includes a memory and a video coder. The memory stores a first video block and a second video block. The first video block and the second video block include sub-blocks. The video coder processes a first sub-block of the first video block according to a first process and a second process, and processes a second sub-block of the first video block according to the first process and the second process after processing the first sub-block of the first video block according to the first process and the second process. Further, the video coder processes a first sub-block of the second video block according to the first process before processing the second sub-block of the first video block according to the first process.

Abstract: Methods and systems for performing at least one of video encoding and video decoding are disclosed. In one implementation, the system includes a controller configured to determine a video standard associated with a portion of the video data, each portion of the video data associated with one of a plurality of video standards. The controller is further configured to provide a set of the filter parameters which are associated with a video standard to be used for at least one of the video encoding and decoding and at least one filter configured to filter at least one reference pixel received from the reference pixel memory based, at least in part, on the provided set of filter parameters.

Abstract: In an example, a method for filtering pixel data in video coding comprises determining a pixel filtering task from a plurality of pixel filtering tasks for filtering the pixel data, wherein each filtering task of the plurality of pixel filtering tasks is based on an instruction set for a programmable instruction set based controller, and executing the determined filtering task on the pixel data.

Abstract: In an example, a method for filtering pixel data in video coding comprises determining a pixel filtering task from a plurality of pixel filtering tasks for filtering the pixel data, wherein each filtering task of the plurality of pixel filtering tasks is based on an instruction set for a programmable instruction set based controller, and executing the determined filtering task on the pixel data.

Abstract: Methods and systems for efficient searching of candidate blocks for inter-coding and/or intra coding are provided. In one innovative aspect, an apparatus for performing motion estimation is provided. The apparatus includes a processor configured to identify a number of candidate blocks of a frame of video data to be searched, at least one candidate block corresponding to a block of another frame of the video data. The processor is further configured to select one or more of the candidate blocks to search based on a distance between the candidate blocks. The processor is also configured to select a method for searching the selected candidate blocks based on a format of the video data. The processor is also configured to estimate the motion for the block of the another frame based on the selected method and the selected candidate blocks.

Abstract: Methods and systems for performing at least one of video encoding and video decoding are disclosed. In one implementation, the system includes a controller configured to determine a video standard associated with a portion of the video data, each portion of the video data associated with one of a plurality of video standards. The controller is further configured to provide a set of the filter parameters which are associated with a video standard to be used for at least one of the video encoding and decoding and at least one filter configured to filter at least one reference pixel received from the reference pixel memory based, at least in part, on the provided set of filter parameters.

Abstract: Systems and methods for interleaving video sub-blocks in video coding are described herein. In one aspect, an apparatus includes a memory and a video coder. The memory stores a first video block and a second video block. The first video block and the second video block include sub-blocks. The video coder processes a first sub-block of the first video block according to a first process and a second process, and processes a second sub-block of the first video block according to the first process and the second process after processing the first sub-block of the first video block according to the first process and the second process. Further, the video coder processes a first sub-block of the second video block according to the first process before processing the second sub-block of the first video block according to the first process.