Patents by Inventor Ling-Hsiu Chou

Ling-Hsiu Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210217866
    Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.
    Type: Application
    Filed: February 18, 2020
    Publication date: July 15, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen Yang Hsueh, Ling Hsiu Chou, Chih-Yang Hsu
  • Publication number: 20180182900
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. The tunneling oxide layer is disposed on the tunneling well. The tunneling oxide layer includes a first tunneling oxide segment having a first thickness, a second tunneling oxide segment having a second thickness, and a third tunneling oxide segment having a third thickness, and the first thickness, the second thickness and the third thickness are different from each other. The charge storage layer is disposed on the tunneling oxide layer, and the control gate is disposed on the charge storage layer.
    Type: Application
    Filed: February 21, 2017
    Publication date: June 28, 2018
    Inventors: Ya-Sheng Feng, Chi-Cheng Huang, Ping-Chia Shih, Hung-Wei Lin, Yu-Chun Chen, Ling-Hsiu Chou, An-Hsiu Cheng
  • Patent number: 10008615
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. The tunneling oxide layer is disposed on the tunneling well. The tunneling oxide layer includes a first tunneling oxide segment having a first thickness, a second tunneling oxide segment having a second thickness, and a third tunneling oxide segment having a third thickness, and the first thickness, the second thickness and the third thickness are different from each other. The charge storage layer is disposed on the tunneling oxide layer, and the control gate is disposed on the charge storage layer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Sheng Feng, Chi-Cheng Huang, Ping-Chia Shih, Hung-Wei Lin, Yu-Chun Chen, Ling-Hsiu Chou, An-Hsiu Cheng
  • Publication number: 20170194511
    Abstract: A non-volatile memory (NVM) device includes a substrate, a charge trapping structure, a first gate electrode and a spacer. The charge trapping structure is disposed on the substrate. The first gate electrode is disposed on the charge trapping structure. The spacer is disposed on at least one sidewall of the first gate electrode and the charge trapping structure. Wherein, the charge trapping structure has a lateral size substantially greater than that of the first gate electrode.
    Type: Application
    Filed: January 27, 2016
    Publication date: July 6, 2017
    Inventors: Yu-Chun Chen, Chun-Hung Cheng, Yu-Chieh Lin, Ya-Sheng Feng, Ping-Chia Shih, Ling-Hsiu Chou
  • Patent number: 9202701
    Abstract: A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 1, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-I Chou, Chi-Cheng Huang, Yu-Chun Chang, Ling-Hsiu Chou, Tseng-Fang Dai, Jheng-Jie Huang, Ping-Chia Shih
  • Patent number: 9129852
    Abstract: A method for fabricating a non-volatile memory semiconductor device is disclosed. The method includes the steps of providing a substrate; forming a gate pattern on the substrate, wherein the gate pattern comprises a first polysilicon layer on the substrate, an oxide-nitride-oxide (ONO) stack on the first polysilicon layer, and a second polysilicon layer on the ONO stack; forming an oxide layer on the top surface and sidewall of the gate pattern; performing a first etching process to remove part of the oxide layer; and performing a second etching process to completely remove the remaining oxide layer.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: September 8, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiang-Chen Lee, Shao-Nung Huang, Wei-Pin Huang, Kuo-Lung Li, Ling-Hsiu Chou, Ping-Chia Shih