Abstract: A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and the cell adjacent each boundary. Nonempty cells are identified as being of specific materials, and empty spaces between cells are represented in the database. For each cell boundary, the database also stores data representing the boundary edge's end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When a point on an edge of a cell is moved, the edge of each neighboring cell that shares that point is also moved. However, the method sizes gate cells of transistors differently from other cells by maintaining the former at predetermined dimensions, with a user-definable override to resize transistors to a percentage of the predetermined dimensions.

Abstract: A routing method for differential current switch (DCS) pairs initially shortens the min/max length window for a first routed rail in order to increase the likelihood that length of the second rail will fall within the window. Next, the routing domain for the first rail is modified so that the first pin exit direction to the route is toward the second pin of the differential current switch pair. A suitable algorithm, such as a prior art mazerouter algorithm, is used to route the first rail along a path restricted to the routing domain. At each proposed via connection for connecting the first rail route from one plane to another, the program accepts the proposed via connection only if there is an available adjacent via for routing the second via. If a via for routing the second rail is not available, the proposed route for the first rail is rejected.