Abstract: A true random-number generator generating a random variable is provided. A first delay circuit delays an input signal to generate a first delayed signal. A second delay circuit delays the first delayed signal to generate a second delayed signal. A first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. A second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. A third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal. An operational circuit generates the random variable and adjusts a count value according to the first sampled signal, the second sampled signal, and the third sampled signal. The operational circuit adjusts the clock signal according to the count value.

Abstract: A detection circuit is provided in the invention. The detection circuit includes a synchronous circuit, a comparison circuit and a fail-signal generating circuit. The comparison circuit is coupled to the synchronous circuit. The comparison circuit compares a target signal with a reference signal to generate a comparison result. The frequency of the reference signal is lower than the frequency of the target signal. The fail-signal generates circuit is coupled to the synchronous circuit and the comparison circuit. The fail-signal receives the comparison circuit. According to the comparison circuit, the fail-signal determines whether the target signal has failed.

Abstract: A true random-number generator generating a random variable is provided. A first delay circuit delays an input signal to generate a first delayed signal. A second delay circuit delays the first delayed signal to generate a second delayed signal. A first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. A second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. A third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal. An operational circuit generates the random variable and adjusts a count value according to the first sampled signal, the second sampled signal, and the third sampled signal. The operational circuit adjusts the clock signal according to the count value.

Abstract: A detection circuit is provided in the invention. The detection circuit includes a synchronous circuit, a comparison circuit and a fail-signal generating circuit. The comparison circuit is coupled to the synchronous circuit. The comparison circuit compares a target signal with a reference signal to generate a comparison result. The frequency of the reference signal is lower than the frequency of the target signal. The fail-signal generates circuit is coupled to the synchronous circuit and the comparison circuit. The fail-signal receives the comparison circuit. According to the comparison circuit, the fail-signal determines whether the target signal has failed.