Patents by Inventor Ling Kuey Yang

Ling Kuey Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate
    Patent number: 8354335
    Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 15, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chen-Chin Liu, Lan Ting Huang, Ling Kuey Yang, Po Hsuan Wu
  • APPARATUS AND ASSOCIATED METHOD FOR MAKING A FLOATING GATE CELL WITH INCREASED OVERLAY BETWEEN THE CONTROL GATE AND FLOATING GATE
    Publication number: 20110086482
    Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.
    Type: Application
    Filed: December 22, 2010
    Publication date: April 14, 2011
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chen-Chin Liu, Lan Ting Huang, Ling Kuey Yang, Po Hsuan Wu
  • Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate
    Patent number: 7879708
    Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: February 1, 2011
    Assignee: Macronix International Co. Ltd.
    Inventors: Chen-Chin Liu, Lan Ting Huang, Ling Kuey Yang, Po Hsuan Wu
  • APPARATUS AND ASSOCIATED METHOD FOR MAKING A FLOATING GATE CELL WITH INCREASED OVERLAY BETWEEN THE CONTROL GATE AND FLOATING GATE
    Publication number: 20080121971
    Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.
    Type: Application
    Filed: September 21, 2006
    Publication date: May 29, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chen-Chin Liu, Lan Ting Huang, Ling Kuey Yang, Po Hsuan Wu
  • Bit line selection transistor layout structure
    Patent number: 7286396
    Abstract: A BLT can include a different channel length, channel width, or both to compensate for bit line loading effects. The channel length and/or channel width of the transistor structure can be configured so as to achieve a desired loading. Thus, the bit line transistor structure can improve global metal bit line loading uniformity and provide greater uniformity in bit line bias. Additionally, the greater uniformity in bit line bias can improve reliability.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: October 23, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Ling Kuey Yang, Chen Chin Liu, Lan Ting Huang, Po Hsuan Wu