Patents by Inventor Ling Liao

Ling Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250255893
    Abstract: A chemical compound including Isopropyl-D-glucopyranoside derivatives and its chemical synthesis to prepare the chemical compound. The Isopropyl-D-glucopyranoside derivatives is used for promoting regeneration of injured brain neurons and retinal neurons.
    Type: Application
    Filed: October 25, 2022
    Publication date: August 14, 2025
    Inventors: Linyi CHEN, Yi WANG, Wen-Ling LIAO, Yu-Tang LEE, Ting-Hsuan LU, Yu-Wen HUANG, Chia-Wei LI, Chen WANG, Fang-Yi CHEN, Chuan-Chin CHIAO
  • Publication number: 20250240420
    Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.
    Type: Application
    Filed: April 8, 2025
    Publication date: July 24, 2025
    Inventors: Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Chong Soon LIM, Sughosh Pavan SHASHIDHAR, Ru Ling LIAO, Hai Wei SUN, Han Boon TEO, Jing Ya LI
  • Publication number: 20250240421
    Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.
    Type: Application
    Filed: April 9, 2025
    Publication date: July 24, 2025
    Inventors: Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Chong Soon LIM, Sughosh Pavan SHASHIDHAR, Ru Ling LIAO, Hai Wei SUN, Han Boon TEO, Jing Ya LI
  • Publication number: 20250240410
    Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of horizontal gradient values; derives, as a first parameter, the total sum of the absolute values of horizontal gradient values; derives, as a second parameter, the total sum of the absolute values of vertical gradient values; derives a horizontal-related pixel difference value; derives, as a third parameter, the total sum of the absolute values of horizontal-related pixel difference values; derives a vertical-related pixel difference value; derives, as a fourth parameter, the total sum of the absolute values of vertical-related pixel difference values; and generates a prediction image using the first to fourth parameters.
    Type: Application
    Filed: April 10, 2025
    Publication date: July 24, 2025
    Inventors: Jing Ya LI, Ru Ling LIAO, Chong Soon LIM, Han Boon TEO, Hai Wei SUN, Che Wei KUO, Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA
  • Publication number: 20250234028
    Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.
    Type: Application
    Filed: April 4, 2025
    Publication date: July 17, 2025
    Inventors: Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Ryuichi KANOH, Chong Soon LIM, Ru Ling LIAO, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Han Boon TEO, Jing Ya LI
  • Publication number: 20250233990
    Abstract: An encoder that encodes a current block in a picture includes circuitry and memory. Using the memory, the circuitry: splits the current block into a first sub block, a second sub block, and a third sub block in a first direction, the second sub block being located between the first sub block and the third sub block; prohibits splitting the second sub block into two partitions in the first direction; and encodes the first sub block, the second sub block, and the third sub block.
    Type: Application
    Filed: March 3, 2025
    Publication date: July 17, 2025
    Inventors: Sughosh Pavan SHASHIDHAR, Hai Wei SUN, Chong Soon LIM, Ru Ling LIAO, Han Boon TEO, Jing Ya LI, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Tadamasa TOMA
  • Publication number: 20250233991
    Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.
    Type: Application
    Filed: April 7, 2025
    Publication date: July 17, 2025
    Inventors: Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Chong Soon LIM, Sughosh Pavan SHASHIDHAR, Ru Ling LIAO, Hai Wei SUN, Han Boon TEO, Jing Ya LI
  • Patent number: 12363287
    Abstract: An image encoder includes: circuitry; and a memory coupled to the circuitry. The circuitry, in operation: calculates first values of a current block using intra prediction, the intra prediction being limited to planar mode, the planar mode using multiple reference pixels for each pixel location of the current block; calculates second values of the current block using inter prediction; calculates third values of the current block by weighting the first values and the second values; and encodes the current block using the third values, and in the calculating of the third values, a first weight is applied to the first values and a second weight is applied to the second values, the second weight being different from the first weight.
    Type: Grant
    Filed: May 7, 2024
    Date of Patent: July 15, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Ru Ling Liao, Chong Soon Lim, Jing Ya Li, Han Boon Teo, Hai Wei Sun, Che Wei Kuo, Yusuke Kato, Tadamasa Toma, Kiyofumi Abe, Takahiro Nishi
  • Patent number: 12363320
    Abstract: The present disclosure provides systems and methods for processing video content. The method can include: partitioning, along a partitioning edge, a plurality of blocks associated with a picture into a first partition and a second partition; performing inter prediction on the plurality of blocks, to generate a first prediction signal for the first partition and a second prediction signal for the second partition; and blending the first and second prediction signals for edge blocks associated with the partitioning edge.
    Type: Grant
    Filed: February 23, 2024
    Date of Patent: July 15, 2025
    Assignee: Alibaba Group Holding Limited
    Inventors: Ru-Ling Liao, Jie Chen, Yan Ye, Jiancong Luo
  • Patent number: 12363286
    Abstract: An image encoder includes: circuitry; and a memory coupled to the circuitry. The circuitry, in operation: calculates first values of a current block using intra prediction, the intra prediction being limited to planar mode, the planar mode using multiple reference pixels for each pixel location of the current block; calculates second values of the current block using inter prediction; calculates third values of the current block by weighting the first values and the second values; and encodes the current block using the third values, and in the calculating of the third values, a first weight is applied to the first values and a second weight is applied to the second values, the second weight being different from the first weight.
    Type: Grant
    Filed: May 7, 2024
    Date of Patent: July 15, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Ru Ling Liao, Chong Soon Lim, Jing Ya Li, Han Boon Teo, Hai Wei Sun, Che Wei Kuo, Yusuke Kato, Tadamasa Toma, Kiyofumi Abe, Takahiro Nishi
  • Patent number: 12363350
    Abstract: The present disclosure provides methods for performing training and executing of a multi-density neural network in video processing. An exemplary method comprises: receiving a video stream comprising a plurality of pictures; processing the plurality of pictures using a first branch of a first block in the neural network, wherein the neural network is configured to reduce blocking artifacts in video compression of the video stream and the first branch comprises one or more residual blocks; and processing the plurality of pictures using a second branch of the first block in the neural network, wherein the second branch comprises a down-sampling processing, an up-sampling processing, and one or more residual blocks.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: July 15, 2025
    Assignee: Alibaba Group Holding Limited
    Inventors: Zhao Wang, Changyue Ma, Ru-Ling Liao, Yan Ye
  • Patent number: 12363297
    Abstract: An encoder that encodes a current block in a picture includes circuitry and memory. Using the memory, the circuitry: splits the current block into a first sub block, a second sub block, and a third sub block in a first direction, the second sub block being located between the first sub block and the third sub block; prohibits splitting the second sub block into two partitions in the first direction; and encodes the first sub block, the second sub block, and the third sub block.
    Type: Grant
    Filed: September 6, 2023
    Date of Patent: July 15, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Sughosh Pavan Shashidhar, Hai Wei Sun, Chong Soon Lim, Ru Ling Liao, Han Boon Teo, Jing Ya Li, Takahiro Nishi, Kiyofumi Abe, Ryuichi Kanoh, Tadamasa Toma
  • Publication number: 20250227268
    Abstract: Generative Face Video Compression (“GFVC”) techniques are provided to improve performance of facial video compression. A computing system is configured to compute a relative difference metric describing differences in features between frames, and determining, based on the relative difference metric, whether a current frame can be synthesized without entropy coding, or should be re-coded. A computing system is configured to perform two-stage training to stabilize Generative Adversarial Networks (“GAN”) training in GFVC.
    Type: Application
    Filed: January 2, 2025
    Publication date: July 10, 2025
    Inventors: Renjie Zou, Bolin Chen, Ru-ling Liao, Jie Chen, Yan Ye
  • Publication number: 20250227241
    Abstract: Methods and systems implement application of template-matching-based motion refinement on subblocks of coding blocks. A VVC-standard encoder and a VVC-standard decoder can configure one or more processors of a computing system to obtain sub-templates of each subblock of a coding block from respective motion vectors of neighboring subblocks.
    Type: Application
    Filed: January 2, 2025
    Publication date: July 10, 2025
    Inventors: Jie Chen, Ru-ling Liao, Yan Ye, Xinwei Li
  • Publication number: 20250227292
    Abstract: Methods and systems implement fusion of intra TMP mode with other intra prediction modes that utilize adjacent samples, to improve prediction accuracy. A VVC-standard encoder and a VVC-standard decoder can configure one or more processors of a computing system to apply non-CCP modes on the template of the collocated luma block, and reorder non-CCP modes based on template matching cost; additionally reorder angular modes, such as a subset of efficient angular modes based on the template of the collocated luma block; prune non-CCP modes from the ordered list based on similarity; move a non-CCP mode of the reordered ordered list based on template matching cost difference relative to a predecessor; copy and reorder the ordered list of non-CCP modes once for each respective distinctly signaled chroma fusion mode; fuse a chroma DBV mode with a CCP mode; and select a least-cost reordered block vector for chroma DBV mode.
    Type: Application
    Filed: January 2, 2025
    Publication date: July 10, 2025
    Inventors: Xinwei Li, Ru-ling Liao, Jie Chen, Yan Ye
  • Patent number: 12355982
    Abstract: A VVC-standard encoder and a VVC-standard decoder are provided, implementing a decoder-side chroma intra prediction mode gradient-based derivation method, which improves coding efficiency of chroma intra prediction, thereby saving on signaling cost. A VVC-standard decoder configures one or more processors of a computing system to derive one of multiple possible chroma intra prediction modes by computing gradients of adjacent luma samples and chroma samples of a current chroma block. With minimal increase in signaling cost, the VVC-standard coding and decoding processes are enhanced to base intra prediction modes for chroma blocks on collocated luma block-adjacent reconstructed luma samples adjacent reconstructed chroma samples, enabling prior computational work done on coding and decoding adjacent blocks to be referenced. In this fashion, coding gains can be achieved in matching texture characteristics of the current chroma block based on a texture gradient including adjacent blocks.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: July 8, 2025
    Assignee: Alibaba (China) Co., Ltd
    Inventors: Xinwei Li, Ru-Ling Liao, Jie Chen, Yan Ye
  • Publication number: 20250216624
    Abstract: Scalable heterogeneous (hybrid) silicon photonic (SiPh) wavelength division multiplexing laser source architectures suitable as a fiber-coupled external photonic IC (PIC) source for high-bandwidth communication between computing resources. Hybrid-silicon laser sources may be arrayed over a silicon substrate into physically separate banks of lasers, each bank spanning a different range of consecutive wavelength channels and each bank including physically separated odd and even channel groups within a channel range. Optical signals generated by each channel group are passed to a multi-mode interference (MMI) coupler that multiplexes the channel group split across some number of output streams that may be limited to maintain sufficient output power for a given application. The odd channeled multiplexed signals and the even channeled multiplexed signals are passed to interleavers that generate a full spectrum output signal for each bank. Output signals from all banks exit the PIC through an output coupler.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Saeed FATHOLOLOUMI, Ling LIAO, Pegah SEDDIGHIAN, Faraz MONIFI
  • Patent number: 12348724
    Abstract: The present disclosure provides methods and systems for fusing chroma intra prediction modes. An exemplary method includes: generating a plurality of predicted chroma samples associated with a pixel, by using a plurality of chroma intra prediction modes respectively; and determining a first predicted chroma sample, based on a weighted sum of the plurality of predicted chroma samples.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: July 1, 2025
    Assignee: Alibaba Innovation Private Limited
    Inventors: Xinwei Li, Ru-Ling Liao, Jie Chen, Yan Ye
  • Patent number: 12347764
    Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.
    Type: Grant
    Filed: June 3, 2024
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Li-Ling Liao, Ming-Chih Yew, Chia-Kuei Hsu, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20250211795
    Abstract: The present disclosure provides a computer-implemented method for encoding video. The method includes: determining whether a coded video sequence (CVS) contains equal number of profile, tier and level (PTL) syntax structures and output layer sets (OLSs); and in response to the CVS containing equal number of PTL syntax structures and OLSs, coding the bitstream without signaling a first PTL syntax element specifying an index, to a list of PTL syntax structures in the VPS, of a PTL syntax structure that applies to a corresponding OLS in the VPS.
    Type: Application
    Filed: March 7, 2025
    Publication date: June 26, 2025
    Inventors: Jie CHEN, Jiancong LUO, Yan YE, Ru-Ling LIAO