Abstract: A package structure is provided. The package structure includes a redistribution structure and a first semiconductor die over the redistribution structure. The package structure also includes a wall structure laterally surrounding the first semiconductor die and the wall structure includes a plurality of partitions separated from one another. The package structure also includes an underfill material between the wall structure and the first semiconductor die. The package structure also includes a molding compound encapsulating the wall structure and the underfill material.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Abstract: A VVC-standard encoder and a VVC-standard decoder are provided, implementing a decoder-side chroma intra prediction mode gradient-based derivation method, which improves coding efficiency of chroma intra prediction, thereby saving on signaling cost. A VVC-standard decoder configures one or more processors of a computing system to derive one of multiple possible chroma intra prediction modes by computing gradients of adjacent luma samples and chroma samples of a current chroma block. With minimal increase in signaling cost, the VVC-standard coding and decoding processes are enhanced to base intra prediction modes for chroma blocks on collocated luma block-adjacent reconstructed luma samples adjacent reconstructed chroma samples, enabling prior computational work done on coding and decoding adjacent blocks to be referenced. In this fashion, coding gains can be achieved in matching texture characteristics of the current chroma block based on a texture gradient including adjacent blocks.

Abstract: The present disclosure provides methods and systems for fusing chroma intra prediction modes. An exemplary method includes: generating a plurality of predicted chroma samples associated with a pixel, by using a plurality of chroma intra prediction modes respectively; and determining a first predicted chroma sample, based on a weighted sum of the plurality of predicted chroma samples.

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, determines whether a first block is available and whether a second block is available, the first block and the second block being defined relative to a current block to be processed; selects a context model based on whether the first block is available, whether the second block is available, which of inter prediction and intra prediction is to be applied to the first block, and which of inter prediction and intra prediction is to be applied to the second block; and encodes, using the context model selected, a parameter indicating which of intra prediction and inter prediction is to be applied to the current block.

Abstract: Technologies for beam expansion and collimation for photonic integrated circuits (PICs) are disclosed. In one embodiment, an ancillary die is bonded to a PIC die. Vertical couplers in the PIC die direct light from waveguides to flat mirrors on a top side of the ancillary die. The flat mirrors reflect the light towards curved mirrors defined in the bottom surface of the ancillary die. The curved mirrors collimate the light from the waveguides. In another embodiment, a cavity is formed in a PIC die, and curved mirrors are formed in the cavity. Light beams from waveguides in the PIC die are directed to the curved mirrors, which collimate the light beams.

Abstract: The present disclosure provides methods for picture processing. The method can include: receiving a bitstream comprising a set of pictures; determining, according to the received bitstream, whether a virtual boundary is signaled at a sequence level for the set of pictures; in response to the virtual boundary being signaled at the sequence level, determining a position of the virtual boundary for the set of pictures, the position being bounded by a range signaled in the received bitstream; and disabling in-loop filtering operations across the virtual boundary.

Abstract: The present disclosure provides systems and methods for video coding. The systems include, for example, an image encoder comprising: circuitry; and a memory coupled to the circuitry, wherein the circuitry, in operation, performs the following: predicting a first block of prediction samples for a current block of a picture, wherein predicting the first block of prediction samples includes at least a prediction process with a motion vector from a different picture; padding the first block of prediction samples to form a second block of prediction samples, wherein the second block is larger than the first block; calculating at least a gradient using the second block of prediction samples; and encoding the current block using at least the calculated gradient.

Abstract: The present disclosure provides a computer-implemented method for encoding or decoding video. The method includes encoding or decoding, in a plurality of picture parameter sets (PPS) associated with pictures of a coded layer video sequence (CLVS), corresponding first PPS flags indicating whether pictures are allowed to be partitioned into a plurality of tiles or slices. In a first PPS, a corresponding first PPS flag with a first value indicates a first picture of the CLVS is unpartitioned, and in a second PPS, another corresponding first PPS flag with a second value being different from the first value indicates that a second picture of the CLVS is allowed to be partitioned.

Abstract: An encoder which includes circuitry and memory. Using the memory, the circuitry generates a list which includes candidates for a first motion vector for a first partition. The list has a maximum list size and an order of the candidates, and at least one of the maximum list size or the order of the candidates is dependent on at least one of a partition size or a partition shape of the first partition. The circuitry selects the first motion vector from the candidates included in the list; encodes an index indicating the first motion vector among the candidates in the list into the bitstream based on the maximum list size; and generates the predicted image for the first partition using the first motion vector.

Abstract: An encoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value. The circuitry, responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction. The circuitry, in operation, splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter; splits the block into a plurality of sub blocks in a second direction parallel to the second shorter side of the block when the ternary split process is not allowed; and encodes the plurality of sub blocks.

Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.

Abstract: Semiconductor devices including fin-shaped isolation structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; a shallow trench isolation (STI) region over the semiconductor substrate adjacent the fin; and a dielectric fin structure over the STI region, the dielectric fin structure extending in a direction parallel to the fin, the dielectric fin structure including a first liner layer in contact with the STI region; and a first fill material over the first liner layer, the first fill material including a seam disposed in a lower portion of the first fill material and separated from a top surface of the first fill material, a first carbon concentration in the lower portion of the first fill material being greater than a second carbon concentration in an upper portion of the first fill material.

Abstract: A method of encoding a video sequence into a bitstream is provided. The method includes: receiving a video sequence; and encoding one or more pictures of the video sequence; wherein the encoding includes: signaling a first flag in a slice header to indicate whether an active reference index number is present in a slice header; in response to the first flag indicating that the active reference index number is present, determining a number of entries of reference picture list 0, and signaling an active reference index number of reference picture list 0 in the slice header for P and B slices; and determining a number of entries of reference picture list 1, and signaling an active reference index number of reference picture list 1 in the slice header for B slice.

Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.

Abstract: The present disclosure provides methods and apparatuses for controlling a coding mode for video data. The methods and apparatuses include receiving a bitstream of video data; enabling or disabling a coding mode for a video sequence, based on a first flag in the bitstream; and determining whether controlling of the coding mode is enabled or disabled at a level lower than a sequence level, based on a second flag in the bitstream.

Abstract: A semiconductor device and a method of forming the same are provided. A device includes a substrate, a first isolation structure over the substrate, a first fin and a second fin over the substrate and extending through the first isolation structure, and a hybrid fin extending into the first isolation structure and interposed between the first fin and the second fin. A top surface of the first fin and a top surface of the second fin are above a top surface of the first isolation structure. A top surface of the hybrid fin is above the top surface of the first isolation structure. The hybrid fin includes an upper region, and a lower region under the upper region. The lower region includes a seam. A topmost portion of the seam is below the top surface of the first fin and the top surface of the second fin.

Abstract: The present disclosure provides a computer-implemented method for encoding video. The method includes coding one or more first flags in a sequence parameter set (SPS) of a bitstream, and coding at least one second flag in the SPS if one or more coding modes are enabled for a video sequence associated with the SPS. The one or more first flags indicate whether the one or more coding modes are enabled for the video sequence. The at least one second flag indicates whether a multi-level control is activated for the one or more coding modes.

Abstract: The present disclosure provides methods, apparatus and non-transitory computer readable medium for processing video data. According to certain disclosed embodiments, a method includes: determining a set of parameters from a plurality of sets of parameters wherein the set of parameters includes a scaling factor; determining a predicted sample value of a first chroma component based on the set of the parameters, a reconstructed sample value of a luma component and a reconstructed sample value of a second chroma component; and signaling an index associated with the set of parameters in a bitstream.