Abstract: A data-driven audio codec system that involves producing multiple compressed streams comprising encoded information (e.g., codeword indices) at different time scales (time intervals or frequency). This may allow for separation of different properties of speech, such as content and aspects of style (prosody), into the different compressed streams without explicitly enforcing it, i.e., in an unsupervised manner. Speech audio is encoded to produce a plurality of encoded streams comprising encoded information for the speech audio at different time scales. The plurality of encoded streams are decoded to generate output audio.

Abstract: A memory cell structure includes a transistor structure and a capacitor structure, where the capacitor structure includes a hydrogen absorption layer. The hydrogen absorption layer absorbs hydrogen, which prevents or reduces the likelihood of the hydrogen diffusing into an underlying metal-oxide channel of the transistor structure. In this way, the hydrogen absorption layer minimizes and/or reduces the likelihood of hydrogen contamination in the metal-oxide channel, which may enable a low current leakage to be achieved for the memory cell structure and reduces the likelihood of data corruption and/or failure of the memory cell structure, among other examples.

Abstract: A method controls the duty cycle distortion of clock signals. An electronic device obtains an input clock signal and generates a first output voltage and a second output voltage from the input clock signal. The first output voltage has a first direct current (DC) voltage level indicating, in real time, a first duty cycle length of high voltage duty cycles of the input clock signal. The second output voltage has a second DC voltage level indicating, in real time, a second duty cycle length of low voltage duty cycles of the input clock signal. The difference between the first and second DC voltage levels corresponds to the duty cycle distortion level of the input clock signal. A duty cycle control signal is generated based on the difference between the first and second DC voltage levels to control the high voltage duty cycles of the input clock signal.

Abstract: A method controls duty cycle distortion of clock signals. An electronic device obtains an input clock signal having a first frequency and a sampling clock signal having a second frequency that is lower than the first frequency. The sampling clock signal has a random noise distribution. The sampling clock signal is applied to sample high voltage duty cycles and low voltage duty cycles of the input clock signal for a duration of time to obtain a sampling result. The electronic device determines a duty cycle distortion level of the input clock signal in the duration of time based on the sampling result. A duty cycle control signal is generated based on the duty cycle distortion level to control the high voltage duty cycles of the input clock signal.

Abstract: The present invention relates to unsupervised tracking technology, specifically an unsupervised tracking model training strategy based on contrastive loss. The method comprises: S1: forming a constrained SSCI module using the relation between objects within a video frame and between adjacent video frames; S2: setting features of different objects in each frame as negative samples, and similar adjacent frame objects as positive sample pairs, constructing contrastive loss; S3: constraining embedded features (E_t) by variable loss based on self-supervised contrastive loss. This invention provides a contrastive loss-based training strategy for unsupervised multi-object tracking, leveraging the prior that objects in a frame must be different to enhance object similarity, and using self-supervised learning to match similar objects in short-interval frames as positive samples to boost cross-frame feature expression.

Abstract: A light emitting diode epitaxial structure and a light emitting diode are provided. The light emitting diode epitaxial structure includes a substrate, and an N-type semiconductor layer, an intermediate layer, a multi-quantum well layer and a P-type semiconductor layer which are sequentially arranged on the substrate, wherein the intermediate layer is doped with a n-type impurity, and a doping concentration of the n-type impurity is ?4×1018 atoms/cm3. In a specific implementation of the present disclosure, the n-type impurity is Si, and the intermediate layer is a GaN layer doped with Si.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: A method controls duty cycle distortion of clock signals. An electronic device obtains an input clock signal having a first frequency and a sampling clock signal having a second frequency that is lower than the first frequency. The sampling clock signal has a random noise distribution. The sampling clock signal is applied to sample high voltage duty cycles and low voltage duty cycles of the input clock signal for a duration of time to obtain a sampling result. The electronic device determines a duty cycle distortion level of the input clock signal in the duration of time based on the sampling result. A duty cycle control signal is generated based on the duty cycle distortion level to control the high voltage duty cycles of the input clock signal.

Abstract: Controlling Duty Cycle Distortion with a Mixed-Signal Circuit A method controls the duty cycle distortion of clock signals. An electronic device obtains an input clock signal and generates a first output voltage and a second output voltage from the input clock signal. The first output voltage has a first direct current (DC) voltage level indicating, in real time, a first duty cycle length of high voltage duty cycles of the input clock signal. The second output voltage has a second DC voltage level indicating, in real time, a second duty cycle length of low voltage duty cycles of the input clock signal. The difference between the first and second DC voltage levels corresponds to the duty cycle distortion level of the input clock signal. A duty cycle control signal is generated based on the difference between the first and second DC voltage levels to control the high voltage duty cycles of the input clock signal.

Abstract: An integrated chip including a gate layer. An insulator layer is over the gate layer. A channel structure is over the insulator layer. A pair of source/drains are over the channel structure and laterally spaced apart by a dielectric layer. The channel structure includes a first channel layer between the insulator layer and the pair of source/drains, a second channel layer between the insulator layer and the dielectric layer, and a third channel layer between the second channel layer and the dielectric layer. The first channel layer, the second channel layer, and the third channel layer include different semiconductors.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: Presented herein are systems and methods for generating a multi-view focused video stream. The methods involve obtaining at least one video stream of a first participant in an online video communication session between at least the first participant at a first endpoint and a second participant at a second endpoint; determining a bounding region of at least one element in the video stream; generating a focused video stream from the video stream that includes a focused view of the at least one element within the bounding region; and presenting the focused video stream on the second endpoint to at least the second participant.

Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.

Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a first oxide material having a first sidewall and a second sidewall, a first spacer layer in contact with the first sidewall of the first oxide material, the first spacer layer having a first conductivity type, a second spacer layer in contact with the second sidewall of the first oxide material, wherein the second spacer layer has the first conductivity type. The memory device also includes a channel layer having a second conductivity type that is opposite to the first conductivity type, wherein the channel layer is in contact with the first oxide material, the first spacer layer, and the second spacer layer. The memory device further includes a ferroelectric layer in contact with the channel layer.

Abstract: A disclosed semiconductor structure may include an interposer, a first semiconductor die electrically coupled to the interposer, a packaging substrate electrically coupled to the interposer, and a capping layer covering one or more of a first surface of the first semiconductor die and a second surface of the packaging substrate. The capping layer may be formed over respective surfaces of each of the first semiconductor die and the packaging substrate. In certain embodiments, the capping layer may be formed only on the first surface of the first semiconductor die and not formed over the package substrate. In further embodiments, the semiconductor structure may include a second semiconductor die, such that the capping layer covers a surface of only one of the first semiconductor die and the second semiconductor die. The semiconductor structure may include a molding compound die frame that is partially or completely covered by the capping layer.

Abstract: Provided are a light-emitting diode and a semiconductor device.

Abstract: Presented herein are systems and methods for generating a multi-view focused video stream. The methods involve obtaining at least one video stream of a first participant in an online video communication session between at least the first participant at a first endpoint and a second participant at a second endpoint; determining a bounding region of at least one element in the video stream; generating a focused video stream from the video stream that includes a focused view of the at least one element within the bounding region; and presenting the focused video stream on the second endpoint to at least the second participant.

Abstract: A ferroelectric memory device includes a semiconductor structure, a stack structure disposed on the semiconductor structure and including multiple dielectric layers and multiple conductive layers that are alternatingly stacked, and multiple memory arrays extending through the stack structure. Each of the memory arrays includes two spaced-apart memory segments connecting to the stack structure, multiple spaced-apart channel portions each being connected to a corresponding one of the memory segments, and multiple pairs of source/bit lines that are spaced apart from each other. Each of the pairs of the source/bit lines is connected between corresponding two of the channel portions. The ferroelectric memory device further includes multiple carrier structures each being connected to one of the source/bit lines in a corresponding one of the pairs of the source/bit lines, and being separated from the other one of the source/bit lines in the corresponding one of the pairs of the source/bit lines.

Abstract: An apparatus including an interface and a processor. The interface may be configured to receive video frames generated by a plurality of capture devices. The processor may be configured to perform operations to detect objects in the video frames received from a first of the capture devices, determine depth information corresponding to the objects detected, determine blending lines in response to the depth information, perform video stitching operations on the video frames from the capture devices based on the blending lines and generate panoramic video frames in response to the video stitching operations. The blending lines may correspond to gaps in a field of view of the panoramic video frames. The blending lines may be determined to prevent the objects from being in the gaps in the field of view. The panoramic video frames may be generated to fit a size of a display.