Abstract: A display substrate includes a substrate, and first active layers, a first functional layer, a second active layer, a second functional layer and an interlayer dielectric layer stacked in sequence on the substrate. The display substrate further includes first vias, second vias and third vias. The first vias each penetrate at least a portion of the second functional layer and at least a portion of the first functional layer, and each expose a partial surface of a first active layer. The second vias each penetrate the interlayer dielectric layer, and are respectively communicated with the first vias. The third vias each penetrate the interlayer dielectric layer and at least another portion of the second functional layer, and each expose a partial surface of the second active layer. The first vias are formed before the interlayer dielectric layer, and the third vias are formed later than the interlayer dielectric layer.

Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels, first data lines, and first power signal lines. The sub-pixel includes a light emitting element including a second electrode. The sub-pixel includes a first connecting portion including a first sub-connecting portion and a first block. The second electrode is overlapped with the first data line, the first power signal line and the first connecting portion, the first power signal line and the first data line are located at both sides of the first connecting portion. A ratio of a minimum distance between edges of the first sub-connecting portion and the first data line which are close to each other to a minimum distance between edges of the first block and the first power signal line which are close to each other is in a range from 0.8 to 1.2.

Abstract: Methods, systems, and devices for address mappings for random access operations are described. A portion of a L2P table may be loaded (e.g., to a buffer) upon receiving a write command (e.g., a random write command). In some instances, one or more entries (e.g., one or more mappings) included in the portion of the L2P table may be updated based on the write command. The portion of the L2P table may be maintained in the buffer during subsequent access operations, such as random read operations. The subsequent access operations may utilize the portion of the L2P table to access a memory device.

Abstract: Provided are a pixel driving circuit, a display panel and a driving method. The pixel driving circuit includes: a driver transistor, a light-emitting device, a compensation capacitor, a threshold compensation sub-circuit, a data writing sub-circuit, a conduction control sub-circuit and a light-emitting control sub-circuit. The threshold compensation sub-circuit, in response to a signal at the compensation signal terminal, provides the threshold voltage of the driver transistor to the first end of the compensation capacitor; the conduction control sub-circuit, in response to the signal at the conduction control terminal, establishes the conducting path between the power signal terminal and the second end of the compensation capacitor; and the light-emitting control sub-circuit, in response to the signal at the light-emitting control signal terminal, provides the drive current generated by the driver transistor to the light-emitting device.

Abstract: A display substrate, a manufacturing method therefor, and a display apparatus are disclosed. The display substrate includes a display area (100), a bonding area (200) and a bezel area (300). On a plane perpendicular to the display substrate, the display substrate includes a base substrate (101) and a driving circuit layer (102). The substrate (101) at least includes a base conductive layer disposed between a first flexible layer (10A) and a second flexible layer (10C), the base conductive layer at least includes a first connection line (70), the driving circuit layer (102) at least includes a data signal line (60) and a second connection line (80), the second connection line (80) is connected to the first connection line (70) through a first lapping via (DV1), the data signal line (60) is connected to the second connection line (80) through a second lapping via (DV2).

Abstract: The present disclosure relates to the field of display technology, and provides a display panel and a display device. The display panel includes a first display area and a second display area, and further includes a plurality of first pixel islands. The first pixel islands are in the first display area and include: at least one first light-emitting unit; at least one first pixel driving circuit, arranged in a one-to-one correspondence with the at least one first light-emitting unit, and configured to provide a driving current to a first light-emitting unit corresponding thereto; and a plurality of first signal line segments configured to provide signals to the at least one first pixel driving circuit.

Abstract: The present disclosure provides a display substrate, a display apparatus and a manufacturing method of a display substrate, including a base substrate; a plurality of sub-pixels are arranged in array on the base substrate, where at least one of the sub-pixels includes at least two light-emitting regions, and light-emitting regions of different sub-pixels are arranged in isolation in the first direction and the second direction, the first direction is an anti-peeping direction, and the second direction is perpendicular to the first direction; and a plurality of light-shielding structures arranged at a light-emitting side of the plurality of sub-pixels, where an orthographic projection of the light-shielding structure on the base substrate extends in the second direction between adjacent light-emitting regions, and the orthographic projection of the light-shielding structure on the base substrate and a corresponding light-emitting region have a first distance in the first direction.

Abstract: Disclosed are a display substrate, a display apparatus and an electronic apparatus, the display substrate includes a base substrate and a plurality of sub-pixels disposed on the base substrate, at least one sub-pixel includes a pixel drive circuit, at least one pixel drive circuit includes a plurality of first-type transistors (M1) and a plurality of second-type transistors (M2), an orthographic projection of at least one first-type transistor (M1) on the base substrate is at least partially overlapped with an orthographic projection of at least one second-type transistor (M2) on the base substrate.

Abstract: A pixel circuit includes a driving sub-circuit, a first voltage writing sub-circuit, a second voltage writing sub-circuit, a writing control sub-circuit, a coupling sub-circuit, a first reset sub-circuit, and a storage sub-circuit. The first voltage writing sub-circuit is configured to write a data signal provided by the data line (DL) to a third node (N3) under the control of a first scan line (GL1) in a data writing stage. The second voltage writing sub-circuit is configured to write a threshold voltage of the driving sub-circuit to the third node (N3) under the control of a compensation control line (GP) in a threshold compensation stage. The writing control sub-circuit is configured to conduct the third node (N3) and a fourth node (N3). The coupling sub-circuit is configured to couple a signal written to the fourth node (N4) to the first node (N1).

Abstract: The embodiments of the present disclosure provide a display panel, a display device and a driving control method. The display panel includes: a shift register unit and output control signal lines coupled to the shift register unit, where the output control signal lines are disposed between the shift register unit coupled thereto and a display region of the display panel, and the shift register unit includes: a shift register, configured to output a cascade signal through a cascaded output terminal; an output circuit, coupled to the shift register, and configured to control a driving output terminal to output a gate scanning signal according to a signal of an output control signal terminal and a signal of a first reference signal terminal, where the output control signal terminal is coupled to one of the output control signal lines.

Abstract: A display substrate includes a plurality of circuit units, and at least one circuit unit includes a pixel driving circuit, a sensing circuit and a photosensitive device, wherein the pixel driving circuit includes at least one light emitting control transistor, the sensing circuit at least includes a sensing control transistor, the sensing control transistor is connected to the photosensitive device, the light emitting control transistor and the sensing control transistor are different types of transistors; and in the at least one circuit unit, the light emitting control transistors and the sensing control transistors are connected to the same light emitting signal line.

Abstract: A display substrate, including: a first display area, the first display area including: a plurality of display island regions and a plurality of light-transmitting regions arranged in an array. The first display area satisfies at least one of: the display island regions and the light-transmitting regions being arranged alternately in a row direction, and the display island regions and the light-transmitting regions being arranged alternately in a column direction. A display island region includes: at least one first pixel circuit and at least one first light emitting element, the at least one first pixel circuit being electrically connected to the at least one first light emitting element and configured to drive the at least one first light emitting element to emit light.

Abstract: The present disclosure provides a shift register unit, a display panel, a driving method thereof and a display apparatus. The shift register unit comprises an input sub-circuit, a control sub-circuit, a first output sub-circuit and a second output sub-circuit. The input sub-circuit is configured to provide a signal of an input signal end to a third node; the control sub-circuit is configured to control signals of a first node and a second node; the first output sub-circuit is configured to enable a cascade output end to output a cascade signal; and the second output sub-circuit is configured to enable a driving output end to output a gate scanning signal.

Abstract: A display panel and a display device are provided. The display panel includes a base substrate, a first source-drain layer, a second source-drain layer, an electrode layer, and a pixel definition layer. The first source-drain layer is provided on the base substrate and includes a data line, the second source-drain layer is provided on the first source-drain layer and includes a power line, the electrode layer is provided on the second source-drain layer and includes electrode parts, and the pixel definition layer is provided on the electrode layer and has pixel openings. The pixel opening is provided in correspondence with the electrode part. An orthographic projection of the pixel opening on the base substrate coincides with that of the electrode part. The orthographic projections of at least some of the electrode parts on the base substrate are at least partially overlapped with that of the data line.

Abstract: A display substrate, a drive method and a manufacturing method thereof, and a display apparatus are disclosed. The display substrate includes multiple circuit units, the circuit units at least includes a pixel drive circuit, the pixel drive circuit at least includes a data writing transistor connected to a data signal line; the plurality of circuit units at least comprise a first circuit unit and a second circuit unit, the first circuit unit includes a first pixel drive circuit, the second circuit unit includes a second pixel drive circuit, the first pixel drive circuit and the second pixel drive circuit share a same data writing transistor and are connected to a same data signal line, and the data signal line sequentially provides a first data signal to the first pixel drive circuit and a second data signal to the second pixel drive circuit through the data writing transistor.

Abstract: A display substrate, a driving method thereof, and a display apparatus are disclosed. The display substrate includes a base substrate, K rows of sub-pixels, and a plurality of kinds of signal lines extending along a row direction provided on the base substrate; the quantity of signal lines of a same kind is multiple, a plurality of signal lines of a same kind are arranged at intervals along a column direction, and each row of sub-pixels are electrically connected with one of signal lines of a same kind; on a plane parallel to the display substrate, the row direction intersects the column direction; in at least some of signal lines of at least one kind, each signal line is configured to be electrically connected to at least two rows of sub-pixels, in the signal lines of at least one kind, the quantity of signal lines of a same kind is a positive integer less than K.

Abstract: A pixel circuit includes a first transistor, a third transistor, and a storage capacitor, the pixel circuit further including a base substrate and a first semiconductor layer and a first conductive layer stacked on the base substrate. The first semiconductor layer includes a first active layer of the first transistor and a third active layer of the third transistor. The first conductive layer includes a first electrode plate and a first gate block of the storage capacitor, an overlapping area of the first gate block and the first active layer of the first transistor serves as a gate electrode of the first transistor, the first electrode plate serves as a gate electrode of the third transistor, and an overlapping area of the third active layer of the third transistor and the first electrode plate serves as a channel region of the third transistor.

Abstract: A display substrate includes a base substrate and sub-pixels. The sub-pixel includes a light-emitting element and a driving circuit. The driving circuit includes first to third transistors and a first storage capacitor. The second transistor includes an active portion including a channel portion and first and second electrodes respectively connected to the channel portion on opposite sides of the channel portion. The channel portion includes first and second sub-channel portions and a channel connection portion connected between the first and second sub-channel portions. The display substrate further includes a shielding portion, a layer where the shielding portion is located is on a side of a layer where the active portion of the second transistor is located away from the base substrate. An orthographic projection of the shielding portion on the base substrate at least partially overlaps with an orthographic projection of the channel connection portion on the base substrate.

Abstract: Embodiments of the present disclosure provide an experimental device and a method for determining a blockage type and a main control factor of a polymer injection well. The experimental device includes an injection system, a simulation system, an output collection system, and an information acquisition system. The simulation system includes a remote processor.

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes pixel regions (PD) and blank regions (PB), the pixel region (PD) includes first power supply lines (70) and a second power supply line (80), the first power supply lines (70) are configured to continuously provide high-level signals to a pixel driving circuit, and the second power supply line (80) is configured to continuously provide low-level signals to a patterned cathode (403), each blank region (PB) includes high-voltage power supply connecting lines connected to the first power supply lines (70) in the adjacent pixel regions (PD) and low-voltage power supply connecting lines connected to the second power supply lines (80) in the adjacent pixel regions (PD), the first power supply lines (70) and the high-voltage power supply connecting lines form a high-voltage power supply wiring with a mesh connection structure.