Abstract: A semiconductor structure, a memory device, a semiconductor device and a semiconductor device manufacturing method are provided. The semiconductor structure includes a die, a power bus and a first pad assembly. The power bus is disposed on the die and extends in a predetermined direction. The first pad assembly is arranged on one side of the power bus. The first pad assembly includes at least four pads separated from one another along the predetermined direction by the first, the second and the third gaps. The first gap and the second gap both have a width larger than a width of the third gap and the first pad assembly includes a power pad coupled to the power bus and located between the first gap and the second gap. The power pad and the first and second gaps are all located between opposing ends of the power bus.

Abstract: A chip molding structure, a wafer level chip scale packaging structure and manufacturing methods thereof are disclosed, relating to the technical field of semiconductor production. The method of making a wafer level chip scale packaging structure includes: providing a wafer, comprising a plurality of bottom chips; bonding the wafer with a carrier; dicing the wafer to separate the plurality of bottom chips from a plurality of peripheral portions; removing the plurality of peripheral portions; and molding the plurality of bottom chips with a mold to form the molding structure. By dicing the wafer into independent bottom chips and peripheral portions, with the peripheral portions being removed before molding, the bottom chips may be prevented from being damaged during the molding. Compared with existing technologies, the packaging quality and production yield are improved.

Abstract: A copper pillar bump structure on a copper pillar on a metal pad of a semiconductor device and a method of fabricating thereof are disclosed. The copper pillar bump structure includes: a metal barrier layer formed on the copper pillar. The metal barrier layer has a U-shaped cross section, a central portion of the metal barrier layer covers the top surface of the copper pillar, an opening of the U-shaped cross section faces away from the copper pillar. The copper pillar bump structure further includes a solder layer on the copper pillar and filling the U-shaped cross section. The copper pillar bump structure provides a metal barrier layer having a U-shaped cross section and fills a solder layer in the U-shaped cross section, the metal barrier layer wraps sides of the solder layer, which can improve the non-wetting problem caused by insufficient tin, or the solder bridging problem caused by excessive solder, during a flip die soldering process.

Abstract: A wafer stacking method and structure are provided. The wafer stacking method includes: providing a first wafer, wherein an upper surface of the first wafer includes a first bonding pad configured to connect to a first signal; fabricating a first redistribution layer (RDL) on the first wafer, comprising a first wiring electrically connected to the first bonding pad, and the first wiring includes a first landing pad; bonding a second wafer on the first RDL, wherein the second wafer includes a second bonding pad configured to connect the first signal and located corresponding to the first bonding pad; fabricating a first through silicon via (TSV) with a bottom connected to the first landing pad at a position corresponding to the first landing pad; and fabricating a second RDL on the second wafer to connect the second bonding pad and the first TSV. This wafer stacking method improves the manufacturing yield.

Abstract: A semiconductor structure, a memory device, a semiconductor device and a semiconductor device manufacturing method are provided. The semiconductor structure includes a die, a power bus and a first pad assembly. The power bus is disposed on the die and extends in a predetermined direction. The first pad assembly is arranged on one side of the power bus. The first pad assembly includes at least four pads separated from one another along the predetermined direction by the first, the second and the third gaps. The first gap and the second gap both have a width larger than a width of the third gap and the first pad assembly includes a power pad coupled to the power bus and located between the first gap and the second gap. The power pad and the first and second gaps are all located between opposing ends of the power bus.

Abstract: A wafer stacking method and structure are provided. The wafer stacking method includes: providing a first wafer having an upper surface comprising a first bonding pad configured to connect to a first signal; fabricating a first lower redistribution layer (RDL) and a first upper RDL on the first wafer, with the first lower RDL including a first wiring connected to the first bonding pad, the first upper RDL including a second wiring connected to the first wiring, and the second wiring having a first landing pad; bonding a second wafer on the first upper RDL, wherein an upper surface of the second wafer includes a second bonding pad configured to connect to a second signal and located corresponding to the first bonding pad; and fabricating a first through silicon via (TSV) connected to the first landing pad. The wafer stacking method improves the manufacturing yield of a die.

Abstract: A first substrate, a second substrate, an intermediate and a plurality of particles form a laminated structure. The first substrate has a first conjunction portion and a second conjunction portion, and the second substrate has a third conjunction portion and a fourth conjunction portion which are characterized by a first hardness. The intermediate is disposed between the first substrate and the second substrate. The particles provided with a second hardness greater than the first hardness are coated on the third conjunction portion to contact the first conjunction portion and coated on the fourth conjunction portion to contact the second conjunction portion. A height difference with reference to the base surface of the second substrate exists between the end surface of the third conjunction portion and the end surface of the fourth conjunction portion.

Abstract: A first substrate, a second substrate, an intermediate and a plurality of particles form a laminated structure. The first substrate has a first conjunction portion and a second conjunction portion, and the second substrate has a third conjunction portion and a fourth conjunction portion which are characterized by a first hardness. The intermediate is disposed between the first substrate and the second substrate. The particles provided with a second hardness greater than the first hardness are coated on the third conjunction portion to contact the first conjunction portion and coated on the fourth conjunction portion to contact the second conjunction portion. A height difference with reference to the base surface of the second substrate exists between the end surface of the third conjunction portion and the end surface of the fourth conjunction portion.

Abstract: A first substrate, a second substrate, an intermediate and a plurality of particles form a laminated structure. The first substrate has a first conjunction portion and a second conjunction portion, and the second substrate has a third conjunction portion and a fourth conjunction portion which are characterized by a first hardness. The intermediate is disposed between the first substrate and the second substrate. The particles provided with a second hardness greater than the first hardness are coated on the third conjunction portion to contact the first conjunction portion and coated on the fourth conjunction portion to contact the second conjunction portion. A height difference with reference to the base surface of the second substrate exists between the end surface of the third conjunction portion and the end surface of the fourth conjunction portion.

Abstract: A first substrate, a second substrate, an intermediate and a plurality of particles form a laminated structure. The first substrate has a first conjunction portion and a second conjunction portion, and the second substrate has a third conjunction portion and a fourth conjunction portion which are characterized by a first hardness. The intermediate is disposed between the first substrate and the second substrate. The particles provided with a second hardness greater than the first hardness are coated on the third conjunction portion to contact the first conjunction portion and coated on the fourth conjunction portion to contact the second conjunction portion. A height difference with reference to the base surface of the second substrate exists between the end surface of the third conjunction portion and the end surface of the fourth conjunction portion.