Abstract: A peak current bypass protection control device applicable in MRAM is provided. In a memory unit array formed of a plurality of magnetic memory bit cells, each column of magnetic memory bit cells is connected in parallel with a bypass unit. When the magnetic memory bit cells of the memory unit array are being read/written, at the moment of switching on a switch, the bypass unit connected in parallel to the magnetic memory bit cells allows an instantaneous peak current to be guided out and prevents it from flowing through the magnetic memory bit cells.

Abstract: A read/write control device of resistive type memory includes a first logic unit and a second logic unit. In a bit line driving circuit, the first logic unit is connected to a gate of a first transistor set for outputting a bit line signal, wherein the first transistor set includes one PMOS and one NMOS serially connected to each other. The first logic unit has a pair of input terminals respectively for receiving a column selection signal and receiving a control signal that decides if data “0” is to be written. In a source line driving circuit, the second logic unit is connected to a gate of a second transistor set for outputting a source line signal, wherein the second transistor set includes one PMOS and one NMOS serially connected to each other. The second logic unit has a pair of input terminals respectively for receiving a column selection signal and receiving a control signal that decides if data “1” is to be written.

Abstract: A digital content processing system and a digital content processing method are disclosed. The method includes the steps of: setting identification data and transmission authority of a data access device in the digital content processing system; authenticating the data access device by the digital content processing system according to the identification data when the digital content processing system receives a connection request of the data access device through the communication network; and enabling the data access device to, under control of the digital content processing system, download digital content and/or upload digital content of the data access device according to the transmission authority of the data access device if the data access device passes the authentication. Therefore, with the data access device, a user unfamiliar with operation of computers and/or networks is able to share or receive digital content conveniently.

Abstract: Provided are an advertisement customization system and method applied in a network system, characterized by an advertisement supply platform classifying advertisement data according to the properties thereof; the service supply platform selecting from the classified advertisement data advertisement data corresponding to the service supply platform; the service supply platform providing service data via the network system to the user end device; and the advertisement supply platform providing the corresponding advertisement data to the user end device when the user end device captures the service data provided by the service supply platform. The present invention enables the service supply platform to connect to the advertisement supply platform for customizing the advertisement data related to the service content, thereby increasing the view rate of the advertisement data and increasing advertisers' willingness to advertise.

Abstract: A control pad is split into two sections for output one of three signals selected from the group consisted of 00, 01, and 11 on an integrated circuit. Each section is internally connected to different voltage sources, say Vdd which represents logical “1”, or Vss which represents logical “0”, so that a default output is 1,0. When the split control pad is bonded with outside Vdd or Vss, both sections output “1,1” or “0,0” respectively. One of three possible logic word combinations can be selected to use for an IC.

Abstract: Two memory areas on a wafer are coupled through pass transistors to double the memory capacity of each area and can be sawed to yield two memory chips each with single memory area. A pair of pass transistors are used to couple each dedicated functional pad in both memory areas, when the pass transistors are turned on. The connection between the pass transistor pair can be sawed through to yield single capacity memory dice. The memory capacity can be further increased by coupling more memory areas together with pass transistors.

Abstract: A control pad is split into two sections for output one of three signals selected from the group consisted of 00, 01, and 11 on an integrated circuit. Each section is internally connected to different voltage sources, say Vdd which represents logical “1”, or Vss which represents logical “0”, so that a default output is 1,0. When the split control pad is bonded with outside Vdd or Vss, both sections output “1,1” or “0,0” respectively. One of three possible logic word combinations can be selected to use for an IC.

Abstract: Two memory areas on a wafer are coupled through pass transistors to double the memory capacity of each area and can be sawed to yield two memory chips each with single memory area. A pair of pass transistors are used to couple each dedicated functional pad in both memory areas, when the pass transistors are turned on. The connection between the pass transistor pair can be sawed through to yield single capacity memory dice. The memory capacity can be further increased by coupling more memory areas together with pass transistors.

Abstract: More than one memory areas are connected in parallel to increase the memory capacity when activated. The different memory area in a single unit die is activated by a selector pad which controls a single-pole, double throw switch to enable or disable the different memory areas. The corresponding pads of like memory areas are interconnected.

Abstract: In a "flat cell" read-only memory with a matrix of memory cells, each memory cell is a MOSFET of either a low threshold voltage, which can be turned on when accessed, or a high threshold voltage which cannot be turned on when accessed. Each memory cell is connected between two adjacent columns of local bit lines. These local bit lines are alternately connected to a upper bank selection switch which is connected to a main bit line, and a lower bank selection switch, which is connected to a main virtual ground line. Since these local bit lines are fabricated with diffusion layers which are resistive, the path length, hence the resistance, to access any memory cell in the matrix from the main bit line to the main virtual ground is made the same by this alternate, interdigital local bit line layout. Thus, the access time is made uniform.The layouts of two adjacent banks are mirrored, so that the bank selection switches of two adjacent banks can share a common selection line.