Abstract: A semiconductor component and an electronic device are structured to reduce a gate-drain parasitic capacitance of the semiconductor component. The semiconductor component includes: a substrate; a channel layer and a barrier layer that are sequentially stacked on the substrate; a source and a drain that are disposed on the barrier layer; a first gate and a second gate that are disposed on the barrier layer. The first gate and the second gate are located between the source and the drain, and the second gate is disposed between the first gate and the drain. A first gate field plate is at least partially disposed on a side that is of the first gate and that is close to the drain; and a first source field plate. The first source field plate covers the first gate field plate.

Abstract: This application provides a transistor, including a channel, a source, a drain, a gate, an isolation area disposed on two sides of the channel, and a source field plate located on a side of the gate away from the channel. The source field plate is electrically connected to the source. The source field plate includes a primary field plate and a secondary field plate. The primary field plate partially overlaps the gate. A side part of the primary field plate crosses the gate and extends to the drain along the channel. A first end of the primary field plate crosses the channel along a direction perpendicular to the channel and enters the isolation area. The secondary field plate is located at a boundary between the channel and the isolation area, and extends from the primary field plate to a direction of the source along the channel.

Abstract: A semiconductor device includes a substrate, a gate, a second dielectric layer, and a field plate. The substrate has a first dielectric layer, and a thickness of the first dielectric layer in a first area is greater than a thickness of the first dielectric layer in a second area outside the first area. The gate is located on the substrate and in the first area, the gate includes a first gate structure and a second gate structure, and the second gate structure is formed on a side of the first dielectric layer that is away from the substrate and covers a part of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and is disposed in both the first area and the second area.