Patents by Inventor Lingfei Deng

Lingfei Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mixed threshold flip-flop element to mitigate hold time penalty due to clock distortion
    Patent number: 10181842
    Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: January 15, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Ge Yang, Xi Zhang, Jiani Yu, Lingfei Deng, Hwong-Kwo Lin
  • MIXED THRESHOLD FLIP-FLOP ELEMENT TO MITIGATE HOLD TIME PENALTY DUE TO CLOCK DISTORTION
    Publication number: 20170141768
    Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.
    Type: Application
    Filed: November 18, 2015
    Publication date: May 18, 2017
    Inventors: Ge YANG, Xi ZHANG, Jiani YU, Lingfei DENG, Hwong-Kwo LIN
  • Low clocking power flip-flop
    Patent number: 9525401
    Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: December 20, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Xi Zhang, Hwong-Kwo Lin, Ge Yang, Lingfei Deng
  • LOW CLOCKING POWER FLIP-FLOP
    Publication number: 20160269002
    Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.
    Type: Application
    Filed: March 11, 2015
    Publication date: September 15, 2016
    Inventors: Xi Zhang, Hwong-Kwo Lin, Ge Yang, Lingfei Deng