Patents by Inventor Lingfeng Yuan

Lingfeng Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135315
    Abstract: Systems and methods of analyzing on-shelf price tag labels and products at a product storage facility include an image capture device that captures one or more images of one or more product storage structures at a product storage facility. A computing device communicatively coupled to the image capture device analyzes the images of the product storage structures captured by the image capture device and detects individual price tag labels and individual products located on the product storage structure. Based on the detection of the price tag labels and the products, the computing device also defines separate product storage spaces of the product storage structure, determines which price tag labels are allocated to which of the separate product storage spaces, and associates in a database the price tag labels allocated to the product storage spaces with the products stored in those product storage spaces.
    Type: Application
    Filed: October 20, 2022
    Publication date: April 25, 2024
    Inventors: Jing Wang, Han Zhang, Lingfeng Zhang, Zhaoliang Duan, Mingquan Yuan, Wei Wang, Benjamin R. Ellison, Avinash M. Jade, Raghava Balusu, Zhichun Xiao
  • Publication number: 20240119735
    Abstract: Systems and methods of monitoring inventory of a product storage facility include an image capture device configured to move about the product storage areas of the product storage facility and capture images of the product storage areas from various angles. A computing device coupled to the image capture device obtains the images of the product storage areas captured by the image capture device and processes the obtained images of the product storage areas to detect individual products captured in the obtained images. Based on detection of the individual products captured in the images, the computing device analyzes each of the obtained images to detect one or more adjacent product storage structures (shelves, pallets, etc.) and identifies and selects a single image that fully shows a product storage structure of interest and fully shows each of the products stored on the product storage structure of interest.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: Lingfeng Zhang, Mingquan Yuan, Paul Lewis Lobo, Avinash M. Jade, Zhichun Xiao, William Craig Robinson, JR., Zhaoliang Duan, Wei Wang, Han Zhang, Raghava Balusu, Tianyi Mao
  • Publication number: 20240119749
    Abstract: Systems and methods of monitoring inventory of a product storage facility include an image capture device configured to move about the product storage areas of the product storage facility and capture images of the product storage areas from various angles. A computing device coupled to the image capture device obtains the images of the product storage areas captured by the image capture device and processes the obtained images of the product storage areas to detect individual products captured in the obtained images. Based on detection of the individual products captured in the images, the computing device analyzes each of the obtained images to extract meta data from the packaging the individual products to detect one more keywords and determine the locations of the detected keywords on the packaging, and then utilize this information to predict an identity of the products associated with the packaging.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: Lingfeng Zhang, Han Zhang, Abhinav Pachauri, Amit Jhunjhunwala, Ashlin Ghosh, Avinash Madhusudanrao Jade, Raghava Balusu, Srinivas Muktevi, Mingquan Yuan, Zhaoliang Duan, Zhiwei Huang, Tianyi Mao
  • Publication number: 20140164716
    Abstract: A memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for virtualizing context memory storage and independently controlling access to the context memory without interference from other engine activities. The shared resource management unit overrides a stream of access denials (e.g., NACKs) associated with an access problem. The memory management system and method facilitate efficient and flexible access to memory while controlling translation between virtual and physical memory “spaces”. In one embodiment the memory management system includes a translation lookaside buffer and a fill component. The translation lookaside buffer tracks information associating a virtual memory space with a physical memory space.
    Type: Application
    Filed: August 6, 2013
    Publication date: June 12, 2014
    Inventors: David B. GLASCO, John S. MONTRYM, Lingfeng YUAN, Robert C. KELLER
  • Patent number: 8706975
    Abstract: A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for coordinating context memory storage block binds and independently controlling access to the context memory without interference from other engine activities. In one exemplary implementation the context information is included in a block and the memory management unit binds the block to instance memory. The instance memory can be protected memory. The instance memory can also support multiple channels associated with the plurality of engines. In one exemplary implementation, the instance memory includes a pointer to a page table. The instance memory can also include context save and restore data and each one of the plurality of engines initiates a unique block bind by indicating an association between their engine ID and a given block of instance memory.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: April 22, 2014
    Assignee: Nvidia Corporation
    Inventors: David B. Glasco, John S. Montrym, Lingfeng Yuan
  • Patent number: 8707011
    Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes caching page size data for use in accessing a set-associative translation lookaside buffer (TLB). The technique utilizes a translation lookaside buffer data structure that includes a page size table and a translation lookaside buffer. Upon receipt of a memory access request a page size is looked-up in the page size table utilizing the page directory index in the virtual address. A set index is calculated utilizing the page size. A given set of entries is then looked-up in the translation lookaside buffer utilizing the set index. The virtual address is compared to each TLB entry in the given set. If the comparison results in a TLB hit, the physical address is received from the matching TLB entry.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: April 22, 2014
    Assignee: Nvidia Corporation
    Inventors: David B. Glasco, Lingfeng Yuan
  • Patent number: 8700865
    Abstract: A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example, a memory stores information and instructions for the engines. The shared resource management unit manages memory operations and handles access requests associated with compressed data.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: April 15, 2014
    Assignee: NVIDIA Corporation
    Inventors: James M. Van Dyke, John H. Edmondson, Lingfeng Yuan, Brian D. Hutsell
  • Patent number: 8607008
    Abstract: A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example a memory store information and instructions for the engines. The shared resource management unit independently caches and invalidates page table entries on a per engine basis.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: December 10, 2013
    Assignee: NVIDIA Corporation
    Inventors: David B. Glasco, Lingfeng Yuan
  • Patent number: 8601235
    Abstract: A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a plurality of engines. The shared memory management system independently controls access to the context memory without interference from other engine activities. In one exemplary implementation, the memory management unit tracks an identifier for each of the plurality of engines making a memory access request. The memory management unit associates each of the plurality of engines with particular translation information respectively. This translation information is specified by a block bind operation. In one embodiment the translation information is stored in a portion of instance memory. A memory management unit can be non-blocking and can also permit a hit under miss.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: December 3, 2013
    Assignee: Nvidia Corporation
    Inventors: David B. Glasco, John S. Montrym, Lingfeng Yuan
  • Patent number: 8601223
    Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced page table entries are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can redirect one or more pending page table entry fetch requests to an appropriate coalesced page table entry.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: December 3, 2013
    Assignee: Nvidia Corporation
    Inventor: Lingfeng Yuan
  • Patent number: 8543792
    Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced mappings are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can cache a single coalesced mapping and not all of them. The single cached coalesced mapping may be used to translate all of the virtual addresses to physical addresses for the corresponding contiguous memory space.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: September 24, 2013
    Assignee: Nvidia Corporation
    Inventors: David B. Glasco, Lingfeng Yuan
  • Patent number: 8533425
    Abstract: A shared resource management system and method are described. In one embodiment, a shared resource management system facilitates age based miss replay. In one exemplary implementation, a shared resource management system includes a plurality of engines, and a shared resource a shared resource management unit. The plurality of engines perform processing. The shared resource supports the processing. The shared resource management unit handles multiple outstanding miss requests.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: September 10, 2013
    Assignee: Nvidia Corporation
    Inventor: Lingfeng Yuan
  • Patent number: 8504794
    Abstract: A memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for virtualizing context memory storage and independently controlling access to the context memory without interference from other engine activities. The shared resource management unit overrides a stream of access denials (e.g., NACKs) associated with an access problem. The memory management system and method facilitate access to memory while controlling translation between virtual and physical memory “spaces”. In one embodiment the memory management system includes a translation lookaside buffer and a fill component. The translation lookaside buffer tracks information associating a virtual memory space with a physical memory space. The fill component tracks the status of an access request progress from a plurality of engines independently and faults that occur in attempting to access a memory space.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: August 6, 2013
    Assignee: Nvidia Corporation
    Inventors: David B. Glasco, John S. Montrym, Lingfeng Yuan, Robert C. Keller
  • Patent number: 8352709
    Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes caching segmentation data. The technique utilizes a separate memory for storing a plurality of context specifiers and an MMU. The MMU includes an on-chip cache and a segmentation unit. The MMU receives a location of a particular context specifier and a corresponding context index for each of one or more of the plurality of context specifiers stored in the separate memory. The segmentation unit retrieves the particular context specifier and caches it locally. The segmentation unit also binds the cache location of the particular context specifier to the corresponding context index. After caching one or more context specifiers and generating a corresponding binding, the segmentation unit may receive a memory access request that includes a given context index. A given context specifier that is cached locally is accessed by the segmentation unit using the context index to get a base address.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: January 8, 2013
    Assignee: NVIDIA Corporation
    Inventors: David B. Glasco, John S. Montrym, Lingfeng Yuan
  • Patent number: 8347065
    Abstract: A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a plurality of engines. The shared memory management system independently controls access to the context memory without interference from other engine activities. In one exemplary implementation, the memory management unit tracks an identifier for each of the plurality of engines making a memory access request. The memory management unit associates each of the plurality of engines with particular translation information respectively. This translation information is specified by a block bind operation. In one embodiment the translation information is stored in a portion of instance memory. A memory management unit can be non-blocking and can also permit a hit under miss.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: January 1, 2013
    Inventors: David B. Glasco, John S. Montrym, Lingfeng Yuan
  • Patent number: 7769979
    Abstract: A technique for caching page access parameters, in accordance with one embodiment of the present invention, includes translating a given virtual address to a particular physical address using an address translation data structure. One or more page access parameters related to the particular physical address is stored in a separate page access data structure. The technique may further include accessing the page access data structure to manage access to memory as a function of the page access data.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: August 3, 2010
    Assignee: NVIDIA Corporation
    Inventors: David B. Glasco, Lingfeng Yuan
  • Publication number: 20100106921
    Abstract: A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a plurality of engines. The shared memory management system independently controls access to the context memory without interference from other engine activities. In one exemplary implementation, the memory management unit tracks an identifier for each of the plurality of engines making a memory access request. The memory management unit associates each of the plurality of engines with particular translation information respectively. This translation information is specified by a block bind operation. In one embodiment the translation information is stored in a portion of instance memory. A memory management unit can be non-blocking and can also permit a hit under miss.
    Type: Application
    Filed: December 30, 2009
    Publication date: April 29, 2010
    Applicant: NVIDIA CORPORATION
    Inventors: David B. Glasco, John S. Montrym, Lingfeng Yuan