Abstract: Disclosed is a system and methods for accelerating network protocol processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated protocol processing module that handles steady state network traffic and a software-based processing module that handles infrequent and exception cases in network traffic processing.

Abstract: A method for actively detecting link failures on a high availability backplane architecture. The backplane system includes redundant node boards operatively communicating with redundant switch fabric boards. Uplink ports of the node boards are logically grouped into trunk ports at one end of the communication link with the switch fabric boards. A probe packet is sent, and a probing timer is set whenever either a specified number of bad packets are received, or an idle timer expires. If a response to the probe packet is received before the probe timer expires then the link is deemed valid, otherwise the link is presumed to have failed. Preferably, either the node boards or the switch fabric boards are configured to properly handle a probe pack, which preferably has identical source and destination addresses.

Abstract: A improved Media Access Control (MAC) module specification is presented. The MAC module specification includes configurable support for: a reduced minimum packet size, a reduced inter-frame-gap size, a reduced preamble, receive and transmit clock generation. Benefits may be derived from protocol overhead reductions. Processors adhering to the improved MAC module specification may exchange information at improved bandwidth efficiencies by directly interconnecting respective MAC modules to one another.

Abstract: A method of scheduling queue servicing in a data packet switching environment is provided. The method includes a sequence of cyclical steps. The output queues are scheduled for servicing on a least credit value basis. An output queue is selected from a group of output queues associated with a communications port. The selected output port has at least one Payload Data Unit (PDU) pending transmission and a lowest credit value associated therewith. At least one PDU having a length is transmitted from the selected output queue and the credit value is incremented taking the length of the transmitted PDU into consideration. The transmission of PDUs is divided into transmission periods. Once per transmission period credit values associated with output queues holding PDUs pending transmission are decremented in accordance with transmission apportionments assigned for each output queue. The method emulates weighted fair queue servicing with minimal computation enabling hardware implementation thereof.

Abstract: A protocol enabling the exchange of information between data switching node components and a supervisory management processor is provided. The protocol defines a data frame format, data fields, data field values of a group of command frames. The exchange of information therebetween via the defined frames enables the production of data switching equipment having a generic implementation with a deployable, upgradeable and expandable feature set providing and enhancing support for current and future services.

Abstract: A method of utilizing shared memory resources in switching Protocol Data Units (PDUs) at a data switching node is presented. The method includes reserving: a temporary memory storage portion for storing PDUs prior to queuing for processing thereof, a Class-of-Service memory storage portion to provide support Quality-of-Service guarantees, a shared memory-pool portion and an input port memory storage portion enabling non-blocking input port flow control. Provisions are made for PDU discard decisions to be delayed until after PDU headers are inspected subsequent to the receipt of each PDU. Provisions are made for well-behaved data flows conveyed via an input port to be protected against blocking from misbehaving data flows conveyed via other input ports of the data switching node.

Abstract: A frame forwarding and discard architecture in a Differentiated Services network environment. The architecture comprises a discard logic for discarding a frame from a stream of incoming frames of the network environment in accordance with a discard algorithm, the frame being discarded if a predetermined congestion level in the network environment has been reached, and a predetermined backlog limit of a queue associated with the frame, has been reached. Scheduling logic is also provided for scheduling the order in which to transmit one or more enqueued frames of the network environment.

Abstract: A system and method for implementing a control channel in a packet switched communications network. In a computer network, such as a local area network (LAN) it is known to utilize the Ethernet for distributing communications between stations. The Ethernet employs a standard frame format that includes header frames and, in particular a preamble frame which may be used to provide synchronization information between switching devices or nodes. The preamble frame is not required in a Gigabit Ethernet implementation and the present invention employs a portion of the preamble frame to implement a control channel between switching devices.

Abstract: Apparatus and methods of providing rate control at a user access point of an edge network node of a packet switched communications network are described. Rate control mechanisms are presented in respect of both ingress and egress rate control with quality of service support. Multiple thresholds associated with a single leaky bucket per traffic flow direction enable the mechanism to selectively control traffic rates based on a traffic class priority criteria.

Abstract: An improved combined Switching Data Unit (SDU) queuing discipline for unicast and multicast (Protocol Data Unit) PDU forwarding at a switching node is provided. Multicast SDU descriptor pointers are replicated stored in entries of a First-In/First-Out queue portion of a hybrid output port queue. Unicast SDU descriptor pointers are chained in entries of a linked list queue portion of the hybrid output port queue. Servicing of the hybrid queue uses hybrid queue counters, and inter-departure-counters stored in multicast FIFO queue entries to keep track of the number of unicast SDU linked list entries to be services between the multicast FIFO queue entries. The combined hybrid queue derives storage efficiency benefits from linking unicast PDUs in linked lists and further derives benefits from a simple access to multicast PDU entries.

Abstract: A method for actively detecting link failures on a high availability backplane architecture. The backplane system includes redundant node boards operatively communicating with redundant switch fabric boards. Uplink ports of the node boards are logically grouped into trunk ports at one end of the communication link with the switch fabric boards. A probe packet is sent, and a probing timer is set whenever either a specified number of bad packets are received, or an idle timer expires. If a response to the probe packet is received before the probe timer expires then the link is deemed valid, otherwise the link is presumed to have failed. Preferably, either the node boards or the switch fabric boards are configured to properly handle a probe pack, which preferably has identical source and destination addresses.

Abstract: A high availability backplane architecture. The backplane system includes redundant node boards operatively communicating with redundant switch fabric boards. Uplink ports of the node boards are logically grouped into trunk ports at one end of the communication link with the switch fabric boards. The node boards and the switch fabric boards routinely perform link integrity checks when operating in a normal mode such that each can independently initiate failover to working ports when a link failure is detected. Link failure is detected either by sending a link heartbeat message after the link has had no traffic for a predetermined interval, or after receiving a predetermined consecutive number of invalid packets. Once the link failure is resolved, operation resumes in normal mode.

Abstract: A improved Media Access Control (MAC) module specification is presented. The MAC module specification includes configurable support for: a reduced minimum packet size, a reduced inter-frame-gap size, a reduced preamble, receive and transmit clock generation. Benefits may be derived from protocol overhead reductions. Processors adhering to the improved MAC module specification may exchange information at improved bandwidth efficiencies by directly interconnecting respective MAC modules to one another.

Abstract: Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.

Abstract: A method and implementation are disclosed of partitioning data traffic over a network. The invention includes providing a network having a plurality of priority queues for forwarding data packets where a predetermined number of credits are assigned to each priority queue. Data packets are passed to respective ones of a plurality of priority queues. If at least one of the predetermined number of credits is available, the credit is associated with a respective data packet and the packet is forwarded to a flow queue associated with the respective priority queue. If at least one of the predetermined number of credits is not available, the data packet waits until a credit is returned. When a packet is transmitted, its respectively associated credit is returned to the queue in which it originated for associating with another respective waiting data packet.

Abstract: A media access controller (100) having a power-saving feature. The controller (100) comprises a receive logic circuit for receiving incoming data from a physical interface device (104) and processing the incoming data for transmission to a frame processor (102), and a transmit logic circuit for receiving outgoing data of the frame processor (102) and processing the outgoing data for transmission to the physical interface device (104). A power management control logic (114) operatively connects to each of the receive logic circuit and the transmit logic circuit to control the receive logic circuit and the transmit logic circuit in a first mode or a second mode. The power management control logic (114) controls the media access controller (100) in the first mode to conserve power by stopping operation of substantial portions of both the receive and transmit logic circuits, and in the second mode, which is a full power mode, by running both the receive and transmit logic circuits.

Abstract: A task-based chip-level hardware architecture. The architecture includes a task manager for managing a task with task information, and a task module operatively connected to the task manager for performing the task in accordance with the task information.

Abstract: A protocol enabling the exchange of information between data switching node components and a supervisory management processor is provided. The protocol defines a data frame format, data fields, data field values of a group of command frames. The exchange of information therebetween via the defined frames enables the production of data switching equipment having a generic implementation with a deployable, upgradeable and expandable feature set providing and enhancing support for current and future services.

Abstract: A system and method for implementing a control channel in a packet switched communications network. In a computer network, such as a local area network (LAN) it is known to utilize the Ethernet for distributing communications between stations. The Ethernet employs a standard frame format that includes header frames and, in particular a preamble frame which may be used to provide synchronization information between switching devices or nodes. The preamble frame is not required in a Gigabit Ethernet implementation and the present invention employs a portion of the preamble frame to implement a control channel between switching devices.

Abstract: A method of accessing a shared memory store at a multiported data network node is provided. The method provides for a deterministic access schedule to be used in apportioning processing bandwidth between data ports and bus connected devices used in processing conveyed data. Advantages are derived from eliminating data processing latencies otherwise incurred from: data bus arbitration related to handshaking, arbitration request processing, and switching between read and write memory access cycles.