Abstract: The present disclosure relates to a semiconductor structure and a preparation method thereof, which relates to the field of integrated circuit design and manufacturing technology, where a plurality of bottom electrodes are located on a substrate; a support layer is in direct contact with sidewalls of the plurality of bottom electrodes, and the support layer includes a wavy border; a plurality of openings are located between adjacent bottom electrodes, and arranged in an array at intervals along a first direction and a second direction, where the opening has a first dimension; where when viewed from a top view, the wavy border includes a plurality of peaks and a plurality of valleys, with a distance between adjacent peaks having a second dimension, and the second dimension is greater than the first dimension.