Abstract: A semiconductor die is provided. The semiconductor die includes a D2D transceiver composed of a single die or dual dies. The D2D transceiver includes a first D2D transmitter and a first D2D receiver. The D2D transmitter is configured to send data to a second D2D receiver in a second D2D transceiver of another semiconductor die using a first reference clock signal. The D2D receiver is configured to receive data from a second D2D transmitter in the second D2D transceiver using a second reference clock signal. Through using the embodiments of the disclosure, a transmission solution may be flexibly configured for a multi-application scenario including D2D.

Abstract: The disclosure provides a chipset and a manufacturing method thereof. The chipset includes multiple logic cores and a memory chip. The logic cores respectively have a first device layer and a first substrate layer, and respectively include multiple first bonding elements and a first input/output circuit. The first bonding elements are provided in the first device layer. The first input/output circuit is provided in the first device layer. The memory chip has a second device layer and a second substrate layer, and includes second bonding elements and second input/output circuits. The second bonding elements are arranged in the second device layer. The second input/output circuits are arranged in the second device layer, and are respectively connected to the first input/output circuits of the logic cores.

Abstract: A chip and a chip test method are provided. The chip includes a receiver circuit and a test circuit. The receiver circuit includes a signal receiving unit and a signal bump. The signal bump is coupled to the signal receiving unit. The test circuit is coupled to a circuit node between the signal receiving unit and the signal bump. The test circuit includes a digital-to-analog converter, a first resistor, and a unit gain buffer. A first terminal of the first resistor is coupled to the circuit node. An output terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A first input terminal of the unit gain buffer is coupled to an output terminal of the digital-to-analog converter. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer.

Abstract: A chip and a chip testing method are provided. The chip includes a sending terminal circuit and a test circuit. The sending terminal circuit includes a signal sending unit and a first signal bump. The first signal bump is coupled to the signal sending unit. The test circuit is coupled to a circuit node between the signal sending unit and the first signal bump. The test circuit includes a first resistor, a unit gain buffer, and an analog-to-digital converter. A first terminal of the first resistor is coupled to the circuit node. A first input terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer. An input terminal of the analog-to-digital converter is coupled to the output terminal of the unit gain buffer.

Abstract: A chip and a chip testing method are provided. The chip includes a sending terminal circuit and a test circuit. The sending terminal circuit includes a signal sending unit and a first signal bump. The first signal bump is coupled to the signal sending unit. The test circuit is coupled to a circuit node between the signal sending unit and the first signal bump. The test circuit includes a first resistor, a unit gain buffer, and an analog-to-digital converter. A first terminal of the first resistor is coupled to the circuit node. A first input terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer. An input terminal of the analog-to-digital converter is coupled to the output terminal of the unit gain buffer.

Abstract: A chip and a chip test method are provided. The chip includes a receiver circuit and a test circuit. The receiver circuit includes a signal receiving unit and a signal bump. The signal bump is coupled to the signal receiving unit. The test circuit is coupled to a circuit node between the signal receiving unit and the signal bump. The test circuit includes a digital-to-analog converter, a first resistor, and a unit gain buffer. A first terminal of the first resistor is coupled to the circuit node. An output terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A first input terminal of the unit gain buffer is coupled to an output terminal of the digital-to-analog converter. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer.

Abstract: The present disclosure provides a chipset and a manufacturing method thereof. The chipset includes a logic chip, an input/output chip, and an interposer. The logic chip includes a plurality of first bonding components disposed in the first device layer. The input/output chip includes a plurality of second bonding components disposed in the second device layer. The interposer includes a plurality of third bonding components disposed in the third device layer. The logic chip is directly bonded to the first portion of the plurality of third bonding components of the interposer in a pad-to-pad manner through the first portion of the plurality of first bonding components, and the input/output chip is directly bonded to the second portion of the plurality of third bonding components of the interposer in a pad-to-pad manner through the plurality of second bonding components.

Abstract: A semiconductor die is provided. The semiconductor die includes a D2D transceiver composed of a single die or dual dies. The D2D transceiver includes a first D2D transmitter and a first D2D receiver. The D2D transmitter is configured to send data to a second D2D receiver in a second D2D transceiver of another semiconductor die using a first reference clock signal. The D2D receiver is configured to receive data from a second D2D transmitter in the second D2D transceiver using a second reference clock signal. Through using the embodiments of the disclosure, a transmission solution may be flexibly configured for a multi-application scenario including D2D.

Abstract: The disclosure provides a chipset and a manufacturing method thereof. The chipset includes multiple logic cores and a memory chip. The logic cores respectively have a first device layer and a first substrate layer, and respectively include multiple first bonding elements and a first input/output circuit. The first bonding elements are provided in the first device layer. The first input/output circuit is provided in the first device layer. The memory chip has a second device layer and a second substrate layer, and includes second bonding elements and second input/output circuits. The second bonding elements are arranged in the second device layer. The second input/output circuits are arranged in the second device layer, and are respectively connected to the first input/output circuits of the logic cores.

Abstract: The disclosure provides a clock step control circuit and a method thereof. The clock step control circuit includes a clock divider, a multiplexer, and a controller. The clock divider receives a first clock signal and outputs multiple second clock signals. The multiplexer receives the second clock signals and outputs one of the second clock signals. The controller is coupled to the clock divider and the multiplexer. When the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal. The multiplexer outputs another one of the second clock signals according to the selection signal. The clock step control circuit and the method thereof in the disclosure can appropriately switch the clock signal to output a clock signal with an appropriate clock frequency.

Abstract: A method and system for clearing depth and color buffers in a real time graphics rendering system 10. The method and system are able to improve both depth and color buffer clearing. The method and system may utilize a frame flag, a depth clearing module, and a fast color and frame flag clearing module. The system assigns a frame flag to each pixel, which is used to determine whether the current Z value for the pixel is valid. The frame flag may be attached to Z value in the depth buffer. Instead of filling entire depth and color buffers with background values, the system only fills the holes that were not drawn in the previous frame. The fast color and frame flag clearing module traverses a rectangular area, tile by tile, where a tile is a block of pixels, to determine whether each pixel is background by checking the frame flags that are read from the depth buffer.

Abstract: A method and system for clearing depth and color buffers in a real time graphics rendering system 10. The method and system are able to improve both depth and color buffer clearing. The method and system may utilize a frame flag, a depth clearing module, and a fast color and frame flag clearing module. The system assigns a frame flag to each pixel, which is used to determine whether the current Z value for the pixel is valid. The frame flag may be attached to Z value in the depth buffer. Instead of filling entire depth and color buffers with background values, the system only fills the holes that were not drawn in the previous frame. The fast color and frame flag clearing module traverses a rectangular area, tile by tile, where a tile is a block of pixels, to determine whether each pixel is background by checking the frame flags that are read from the depth buffer.