Abstract: Disclosed herein is a Dynamic Random Access Memory-Based Content-Addressable Memory (DRAM-CAM) architecture and methods relating thereto. The DRAM-CAM architecture can include a memory array, with the data organized into blocks including rows and columns. Input data can be converted into a format with first and second groups of columns. Each first group can correspond to one or more rows of the input data, and each second group can include one or more null columns. A query can be received and loaded into an available column of the second group, and pattern matching can be performed on the data to identify occurrences of elements defined by the query. The pattern matching can be performed concurrently on the first groups of columns and the available columns bit by bit. Results can include a count or location of each identified element.

Abstract: Disclosed are various approaches for bit-serial computing embedded in the DRAM subarray, leveraging the massive parallelism of DRAM row operations. The present disclosure discloses digital techniques that can outperform analog charge-sharing techniques. Digital techniques can use more area but support a wider range of computing primitives, and allow a sequence of logic operations to be performed at higher clock speeds, be-tween slower subarray row reads/writes. The present disclosure describes a range of bit-serial architectures, and evaluate raw performance as well as area and energy efficiency. Results show that the digital architecture demonstrates 20× speedup over CPU, 5× over GPU, and 1.7× over SIMDRAM, an analog architecture.

Abstract: Disclosed herein is a Dynamic Random Access Memory-Based Content-Addressable Memory (DRAM-CAM) architecture and methods relating thereto. The DRAM-CAM architecture can include a memory array, with the data organized into blocks including rows and columns. Input data can be converted into a format with first and second groups of columns. Each first group can correspond to one or more rows of the input data, and each second group can include one or more null columns. A query can be received and loaded into an available column of the second group, and pattern matching can be performed on the data to identify occurrences of elements defined by the query. The pattern matching can be performed concurrently on the first groups of columns and the available columns bit by bit. Results can include a count or location of each identified element.

Abstract: Apparatus includes a plurality of memory cells (e.g., a dynamic random access memory (DRAM)) addressable as rows and columns and a plurality of matching circuits configured to be coupled to respective bit lines associated with the columns A control circuit is configured to store respective reference sequences (e.g., binary-encoded k-mer patterns) in respective ones of the columns, to sequentially provide rows of bits stored in the memory cells and bits of a query to the matching circuits, and to identify one of the reference sequences as corresponding to the query responsive to comparisons by the matching circuits.

Abstract: Apparatus includes a plurality of memory cells (e.g., a dynamic random access memory (DRAM)) addressable as rows and columns and a plurality of matching circuits configured to be coupled to respective bit lines associated with the columns A control circuit is configured to store respective reference sequences (e.g., binary-encoded k-mer patterns) in respective ones of the columns, to sequentially provide rows of bits stored in the memory cells and bits of a query to the matching circuits, and to identify one of the reference sequences as corresponding to the query responsive to comparisons by the matching circuits.