Abstract: The present invention provides a method for positioning short circuit failure, used to position the short circuit point between a first metal wire and a second metal wire. The positioning method comprises: measuring the resistance between the first metal wire and the second metal wire, and positioning the first region where the short circuit point is located by a resistance ratio. In the first region, the short circuit point may be gradually approached by periodically cutting the first metal wire and the second metal wire, electrically isolating the cut portions, and performing a plurality of voltage contrast analysis on the first metal wire and the second metal wire based on the principle of the dichotomy, thereby accurately locating the short circuit point. With the positioning method provided by the present invention, the region where the short circuit defect of the nA (nano ampere) level is located may be accurately found from the first metal wire and the second metal wire that are extremely long.

Abstract: A failure positioning method for positioning leakage defect cell between the gate and the active region of transistor cells arranged in an array. The positioning method includes the steps of: measuring the resistance between a first metal wire connecting the active regions and a second metal wire connecting the gates, and positioning a first region where the defect cell is located by resistance ratio; electrically isolating the active region contact holes and the gate contact holes from each other; shorting the gate contact holes in the first region; and performing active voltage contrast analysis on the plurality of columns of transistor cells in the first region to position the leakage defect in the first region by comparing the voltage contrast images. With the positioning method, the transistor cell having a leakage defect at nA level may be accurately found from a plurality of transistor cells arranged in an array.

Abstract: The present invention provides a failure positioning method for positioning leakage defect cell between the gate and the active region of transistor cells arranged in an array. The positioning method comprises: measuring the resistance between a first metal wire connecting the active regions and a second metal wire connecting the gates, and positioning a first region where the defect cell is located by resistance ratio; electrically isolating the active region contact holes and the gate contact holes from each other; shorting the gate contact holes in the first region; and performing active voltage contrast analysis on the plurality of columns of transistor cells in the first region to position the leakage defect in the first region by comparing the voltage contrast images. With the positioning method provided by the present invention, the transistor cell having a leakage defect at nA level may be accurately found from a plurality of transistor cells arranged in an array.

Abstract: The present invention provides a method for positioning short circuit failure, used to position the short circuit point between a first metal wire and a second metal wire. The positioning method comprises: measuring the resistance between the first metal wire and the second metal wire, and positioning the first region where the short circuit point is located by a resistance ratio. In the first region, the short circuit point may be gradually approached by periodically cutting the first metal wire and the second metal wire, electrically isolating the cut portions, and performing a plurality of voltage contrast analysis on the first metal wire and the second metal wire based on the principle of the dichotomy, thereby accurately locating the short circuit point. With the positioning method provided by the present invention, the region where the short circuit defect of the nA (nano ampere) level is located may be accurately found from the first metal wire and the second metal wire that are extremely long.