Abstract: The present invention disclosures a critical dimension error analysis method, comprising: S01: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S02: removing extreme outliers from the critical dimension (CD) values; S03: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD?) values, according to relative error between CD? and CD, dividing the rebuilt critical dimension (CD?) values into scenes and the number of the scenes is A; S04: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S05: modifying machine parameters and masks by the correction model according to above calculation results.

Abstract: A memory and reading, writing and erasing methods thereof. The memory includes: H memory planes arranged in parallel along a first direction, where each memory plane extends in a second direction, and includes M columns of memory strings; each column of memory string extends in a third direction; the first direction, the second direction and the third direction are all different, and H and M are integers greater than zero; each column of memory string includes N rows of memristive memory cells. The memory is also provided with word lines, gating transistors, gating lines, bit lines and a common source line, where memristive memory cells in last rows of all memory strings are connected to the common source line, and the common source line is connected to a reference potential through a reference resistor. Use performance of the memory can be improved.

Abstract: A metrology target includes a first target structure formed within at least one of a first area and a third area of a first layer of a sample, where the first target structure comprises a plurality of first cells containing one or more first cell pattern elements; and a second target structure formed within at least one of a second area and a fourth area of a second layer of the sample, the second target structure comprising a plurality of second cells containing one or more second cell pattern elements.

Abstract: The present invention disclosures a critical dimension error analysis method, comprising: S01: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S02: removing extreme outliers from the critical dimension (CD) values; S03: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD?) values, according to relative error between CD? and CD, dividing the rebuilt critical dimension (CD?) values into scenes and the number of the scenes is A; S04: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S05: modifying machine parameters and masks by the correction model according to above calculation results.

Abstract: An overlay compensation method and a related system are presented. The method includes: acquiring a first offset vector reflecting the relative position between overlay marks of a middle and a bottom target layers; acquiring a second offset vector reflecting the relative position between the overlay marks of a top and the middle target layers; decomposing the first offset vector into a first compensable component and a first uncompensable component; decomposing the second offset vector into a second compensable component and a second uncompensable component; computing minimum values of the first uncompensable component and the second uncompensable component; computing optimized values for the first compensable component and the second compensable component; and computing a third compensable component of a third offset vector reflecting the relative position between the overlay marks of the top and the bottom target layers.

Abstract: An overlay compensation method and a related system are presented. The method includes: acquiring a first offset vector reflecting the relative position between overlay marks of a middle and a bottom target layers; acquiring a second offset vector reflecting the relative position between the overlay marks of a top and the middle target layers; decomposing the first offset vector into a first compensable component and a first uncompensable component; decomposing the second offset vector into a second compensable component and a second uncompensable component; computing minimum values of the first uncompensable component and the second uncompensable component; computing optimized values for the first compensable component and the second compensable component; and computing a third compensable component of a third offset vector reflecting the relative position between the overlay marks of the top and the bottom target layers.