Abstract: The present disclosure relates to an integrated treatment method of two-stage submerged combustion evaporation for organic waste liquid, the organic waste liquid to be disposed flowing into two evaporation chambers in succession for two-stage submerged combustion evaporation. The two evaporation chambers are provided in one evaporation tank and communicate with each other at the bottom of the evaporation tank, the organic waste liquid enters a first evaporation chamber from a raw liquid inlet pipe, and the organic waste liquid flows from the first evaporation chamber to a second evaporation chamber during submerged combustion evaporation. The method has advantages of improving the evaporation concentration efficiency, reducing the numbers of evaporators and transport pipes of all sorts of gases and liquids and saving energy, saving the area occupied and the cost, while simplifying treatment process and facilitating operation management.

Abstract: The present disclosure relates to an integrated treatment method of two-stage submerged combustion evaporation for organic waste liquid, the organic waste liquid to be disposed flowing into two evaporation chambers in succession for two-stage submerged combustion evaporation. The two evaporation chambers are provided in one evaporation tank and communicate with each other at the bottom of the evaporation tank, the organic waste liquid enters a first evaporation chamber from a raw liquid inlet pipe, and the organic waste liquid flows from the first evaporation chamber to a second evaporation chamber during submerged combustion evaporation. The method has advantages of improving the evaporation concentration efficiency, reducing the numbers of evaporators and transport pipes of all sorts of gases and liquids and saving energy, saving the area occupied and the cost, while simplifying treatment process and facilitating operation management.

Abstract: A split gate memory device, a semiconductor device and a manufacturing method thereof are provided. In the split gate memory device, an erasing gate is further disposed, wherein the easing gate and a control gate are respectively disposed on two sides of a floating gate. Thus, an erase operation is implemented by the erasing gate instead of the control gate. Accordingly, electric potential applied to the control gate is reduced. Therefore, hot-electron effect in channel region may be avoided, and performance degradation of the memory caused by the hot-electron effect may be avoided as well. Furthermore, as electric potential applied to the control gate is reduced, a gate oxide layer underneath the control gate may be thinner. Accordingly, manufacturing processes of the control gate and the gate oxide layer and that of the gate and the gate oxide layer of a logic transistor in a periphery circuit may be compatible.

Abstract: A split gate memory device, a semiconductor device and a manufacturing method thereof are provided. In the split gate memory device, an erasing gate is further disposed, wherein the easing gate and a control gate are respectively disposed on two sides of a floating gate. Thus, an erase operation is implemented by the erasing gate instead of the control gate. Accordingly, electric potential applied to the control gate is reduced. Therefore, hot-electron effect in channel region may be avoided, and performance degradation of the memory caused by the hot-electron effect may be avoided as well. Furthermore, as electric potential applied to the control gate is reduced, a gate oxide layer underneath the control gate may be thinner. Accordingly, manufacturing processes of the control gate and the gate oxide layer and that of the gate and the gate oxide layer of a logic transistor in a periphery circuit may be compatible.