Abstract: Disclosed is NOR memory device. The NOR memory device comprises: at least two source/drain contact layers and at least one isolation layer alternately stacked in a vertical direction; a gate structure vertically extending through the source/drain contact layers and the isolation layer; and a semiconductor layer on the periphery of the gate structure; wherein, two of the source/drain contact layers located immediately above and below the isolation layer are respectively connected to two bit/source lines, and form a memory transistor together with the gate structure and the semiconductor layer.

Abstract: Disclosed are NOR memory array, NOR memory and electronic device. The NOR memory array comprises: multiple vertical memory groups arranged in n rows and m columns on a horizontal plane, one vertical memory group includes at least h vertically stacked memory transistors, where n, m, and h are natural numbers greater than 1, wherein, the memory transistors in one vertical memory group share a vertically extended columnar gate structure, part or all of columnar gate structures of vertical memory groups in a same row are connected to a same word line, part or all of memory transistors located at a same stack layer in vertical memory groups in a same column are connected to a same bit line, and an isolation part, for isolating active areas and bit lines of the memory transistors in the adjacent columns, is arranged between adjacent columns of the vertical memory groups.

Abstract: Disclosed are non-volatile memory erasure method and device for solving the problem of unnecessary time expenditure and complex process of the current erasure operation. The method comprises: after receiving an erasure instruction, performing a pre-reading verification on the target erasure area corresponding to the erasure instruction; if the pre-reading verification passes, then performing an erasure operation on the target erasure area; if not, then performing pre-programming verification on the target erasure area, and after the pre-programming verification passes, performing the erasure operation on the target erasure area. The method of the present application can eliminate the unnecessary pre-programming verification process while ensuring the target erasure area is in a full-erasure state before the erasure operation, thus saving erasure time and simplifying the erasure process.

Abstract: Disclosed are non-volatile memory erasure method and device for solving the problem of unnecessary time expenditure and complex process of the current erasure operation. The method comprises: after receiving an erasure instruction, performing a pre-reading verification on the target erasure area corresponding to the erasure instruction; if the pre-reading verification passes, then performing an erasure operation on the target erasure area; if not, then performing pre-programming verification on the target erasure area, and after the pre-programming verification passes, performing the erasure operation on the target erasure area. The method of the present application can eliminate the unnecessary pre-programming verification process while ensuring the target erasure area is in a full-erasure state before the erasure operation, thus saving erasure time and simplifying the erasure process.